FPGA/usb3_pipe
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rename phy to core and USB3PHY to USB3PIPE

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This commit is contained in:
Florent Kermarrec 2019-10-09 12:12:48 +02:00
parent f763c282ea
commit 8bef6fcbc6
4 changed files with 36 additions and 37 deletions
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32
kc705.py
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@ -22,8 +22,8 @@ from liteeth.frontend.etherbone import LiteEthEtherbone
from litescope import LiteScopeAnalyzer
from usb3_pipe.serdes import K7USB3SerDes
from usb3_pipe.phy import USB3PHY
from usb3_pipe.scrambling import Scrambler
from usb3_pipe.core import USB3PIPE
# USB3 IOs -----------------------------------------------------------------------------------------
@ -117,18 +117,18 @@ class USB3SoC(SoCMini):
rx_pads = platform.request(connector + "_rx"))
self.submodules += usb3_serdes
# USB3 PHY ---------------------------------------------------------------------------------
usb3_phy = USB3PHY(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += usb3_phy
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += usb3_pipe
# Idle handshake trigger--------------------------------------------------------------------
idle_start = Signal()
rx_ts2_error = Signal()
rx_ts2_error_d = Signal()
self.comb += rx_ts2_error.eq(usb3_phy.ts.ts2_checker.error)
self.comb += rx_ts2_error.eq(usb3_pipe.ts.ts2_checker.error)
self.sync += rx_ts2_error_d.eq(rx_ts2_error)
self.comb += [
If(usb3_phy.ready,
If(usb3_pipe.ready,
usb3_serdes.source.ready.eq(1),
idle_start.eq(~rx_ts2_error & rx_ts2_error_d),
)
@ -137,7 +137,7 @@ class USB3SoC(SoCMini):
# Scrambler --------------------------------------------------------------------------------
self.submodules.scrambler = scrambler = Scrambler()
self.comb += [
If(usb3_phy.ready,
If(usb3_pipe.ready,
scrambler.sink.valid.eq(1),
scrambler.sink.data.eq(0),
scrambler.source.connect(usb3_serdes.sink)
@ -146,7 +146,7 @@ class USB3SoC(SoCMini):
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(usb3_phy.ready)
self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
@ -156,18 +156,18 @@ class USB3SoC(SoCMini):
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_serdes.rx_polarity,
usb3_phy.lfps.rx_polling,
usb3_phy.lfps.tx_polling,
usb3_pipe.lfps.rx_polling,
usb3_pipe.lfps.tx_polling,
# Training Sequence
usb3_phy.ts.rx_tseq,
usb3_phy.ts.rx_ts1,
usb3_phy.ts.rx_ts2,
usb3_phy.ts.tx_ts2,
usb3_phy.ts.ts2_checker.error,
usb3_pipe.ts.rx_tseq,
usb3_pipe.ts.rx_ts1,
usb3_pipe.ts.rx_ts2,
usb3_pipe.ts.tx_ts2,
usb3_pipe.ts.ts2_checker.error,
# LTSSM
usb3_phy.ltssm.polling_fsm,
usb3_pipe.ltssm.polling_fsm,
idle_start,
# Endpoints

25
pcie_screamer.py
View File

@ -18,7 +18,7 @@ from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer
from usb3_pipe.serdes import A7USB3SerDes
from usb3_pipe.phy import USB3PHY
from usb3_pipe.core import USB3PIPE
# IOs ----------------------------------------------------------------------------------------------
@ -79,8 +79,7 @@ class _CRG(Module):
# USB3SoC ------------------------------------------------------------------------------------------
class USB3SoC(SoCMini):
def __init__(self, platform,
with_analyzer=False):
def __init__(self, platform, with_analyzer=False):
sys_clk_freq = int(133e6)
SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True)
@ -103,12 +102,12 @@ class USB3SoC(SoCMini):
self.submodules += usb3_serdes
# USB3 PHY ---------------------------------------------------------------------------------
usb3_phy = USB3PHY(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += usb3_phy
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += usb3_pipe
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(usb3_phy.ready)
self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
@ -118,17 +117,17 @@ class USB3SoC(SoCMini):
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_serdes.rx_polarity,
usb3_phy.lfps.rx_polling,
usb3_phy.lfps.tx_polling,
usb3_pipe.lfps.rx_polling,
usb3_pipe.lfps.tx_polling,
# Training Sequence
usb3_phy.ts.rx_tseq,
usb3_phy.ts.rx_ts1,
usb3_phy.ts.rx_ts2,
usb3_phy.ts.tx_ts2,
usb3_pipe.ts.rx_tseq,
usb3_pipe.ts.rx_ts1,
usb3_pipe.ts.rx_ts2,
usb3_pipe.ts.tx_ts2,
# LTSSM
usb3_phy.ltssm.polling_fsm,
usb3_pipe.ltssm.polling_fsm,
# Endpoints
usb3_serdes.source,

12
tools/test_analyzer.py
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@ -47,9 +47,9 @@ print("FPGA: " + fpga_id)
# Analyzer dump ------------------------------------------------------------------------------------
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
if sys.argv[1] == "rx_polling":
analyzer.configure_trigger(cond={"soc_usb3_phy_lfps_rx_polling" : 1})
analyzer.configure_trigger(cond={"soc_usb3_pipe_lfps_rx_polling" : 1})
elif sys.argv[1] == "tx_polling":
analyzer.configure_trigger(cond={"soc_usb3_phy_lfps_tx_polling" : 1})
analyzer.configure_trigger(cond={"soc_usb3_pipe_lfps_tx_polling" : 1})
elif sys.argv[1] == "rx_tseq_first_word":
from usb3_pipe.common import TSEQ
TSEQ_FIRST_WORD = int.from_bytes(TSEQ.to_bytes()[0:4], byteorder="little")
@ -57,13 +57,13 @@ elif sys.argv[1] == "rx_tseq_first_word":
"soc_usb3_serdes_source_source_valid" : 1,
"soc_usb3_serdes_source_source_payload_data": TSEQ_FIRST_WORD})
elif sys.argv[1] == "rx_tseq":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_rx_tseq" : 1})
analyzer.configure_trigger(cond={"soc_usb3_pipe_ts_rx_tseq" : 1})
elif sys.argv[1] == "rx_ts1":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_rx_ts1" : 1})
analyzer.configure_trigger(cond={"soc_usb3_pipe_ts_rx_ts1" : 1})
elif sys.argv[1] == "rx_ts2":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_rx_ts2" : 1})
analyzer.configure_trigger(cond={"soc_usb3_pipe_ts_rx_ts2" : 1})
elif sys.argv[1] == "tx_ts2":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_tx_ts2" : 1})
analyzer.configure_trigger(cond={"soc_usb3_pipe_ts_tx_ts2" : 1})
elif sys.argv[1] == "idle_start":
analyzer.configure_trigger(cond={"soc_idle_start" : 1})
elif sys.argv[1] == "now":

4
usb3_pipe/phy.py → usb3_pipe/core.py
View File

@ -9,9 +9,9 @@ from usb3_pipe.lfps import LFPSUnit
from usb3_pipe.training import TSUnit
from usb3_pipe.ltssm import LTSSM
# USB3 PHY -----------------------------------------------------------------------------------------
# USB3 PIPE ----------------------------------------------------------------------------------------
class USB3PHY(Module):
class USB3PIPE(Module):
def __init__(self, serdes, sys_clk_freq):
assert sys_clk_freq > 125e6
self.enable = Signal(reset=1) # i