mirror of
https://github.com/enjoy-digital/usb3_pipe.git
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kc705: use K7USB3SerDes
This commit is contained in:
Florent Kermarrec
parent
15759f556c
commit
9bf8442c9d
113
kc705.py
113
kc705.py
@ -20,9 +20,8 @@ from litex.boards.platforms import kc705
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from litescope import LiteScopeAnalyzer
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from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTX
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from usb3_pipe.common import TSEQ, TS1, TS2
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from usb3_pipe.serdes import K7USB3SerDes
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from usb3_pipe.scrambler import Scrambler
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from usb3_pipe.lfps import LFPSReceiver, LFPSTransmitter
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from usb3_pipe.ordered_set import OrderedSetReceiver, OrderedSetTransmitter
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@ -57,7 +56,7 @@ _usb3_io = [
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_oob = ClockDomain()
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self.clock_domains.cd_usb3_oob = ClockDomain()
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# # #
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@ -65,7 +64,7 @@ class _CRG(Module):
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk156"), 156.5e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_oob, sys_clk_freq/8)
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pll.create_clkout(self.cd_usb3_oob, sys_clk_freq/8)
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# USB3SoC ------------------------------------------------------------------------------------------
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@ -113,80 +112,30 @@ class USB3SoC(SoCMini):
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self.eth_phy.crg.cd_eth_rx.clk,
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self.eth_phy.crg.cd_eth_tx.clk)
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# Transceiver ------------------------------------------------------------------------------
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# refclk
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refclk = Signal()
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refclk_pads = platform.request("sgmii_clock") # Use SGMII clock (FMC does not provide one)
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self.specials += [
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=refclk_pads.p,
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i_IB=refclk_pads.n,
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o_O=refclk)
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]
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# pll
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pll_cls = GTXChannelPLL
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pll = pll_cls(refclk, 125e6, 5e9)
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print(pll)
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self.submodules += pll
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# gtx
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tx_pads = platform.request(connector + "_tx")
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rx_pads = platform.request(connector + "_rx")
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self.submodules.gtx = gtx = GTX(pll, tx_pads, rx_pads, sys_clk_freq,
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data_width=40,
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clock_aligner=False,
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tx_buffer_enable=True,
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rx_buffer_enable=True)
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gtx.add_stream_endpoints()
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gtx.add_controls()
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self.add_csr("gtx")
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gtx._tx_enable.storage.reset = 1 # Enabled by default
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gtx._rx_enable.storage.reset = 1 # Enabled by default
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gtx._tx_polarity.storage.reset = 1
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gtx._rx_polarity.storage.reset = 1
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self.submodules += gtx
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# timing constraints
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gtx.cd_tx.clk.attr.add("keep")
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gtx.cd_rx.clk.attr.add("keep")
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platform.add_period_constraint(gtx.cd_tx.clk, 1e9/gtx.tx_clk_freq)
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platform.add_period_constraint(gtx.cd_rx.clk, 1e9/gtx.rx_clk_freq)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtx.cd_tx.clk,
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gtx.cd_rx.clk)
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# Override GTX parameters/signals for LFPS -------------------------------------------------
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txelecidle = Signal()
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rxelecidle = Signal()
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gtx.gtx_params.update(
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p_PCS_RSVD_ATTR = 0x000000000100, # bit 8 enable OOB
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p_RXOOB_CFG = 0b0000110,
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i_RXOOBRESET = 0,
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i_CLKRSVD = ClockSignal("oob"),
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i_RXELECIDLEMODE = 0b00,
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o_RXELECIDLE = rxelecidle,
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i_TXELECIDLE = txelecidle)
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# USB3 SerDes ------------------------------------------------------------------------------
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usb3_serdes = K7USB3SerDes(platform,
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sys_clk = self.crg.cd_sys.clk,
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sys_clk_freq = sys_clk_freq,
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refclk_pads = platform.request("sgmii_clock"),
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refclk_freq = 125e6,
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tx_pads = platform.request(connector + "_tx"),
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rx_pads = platform.request(connector + "_rx"))
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self.submodules += usb3_serdes
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# LFPS Polling Receive ---------------------------------------------------------------------
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lfps_receiver = LFPSReceiver(sys_clk_freq=sys_clk_freq)
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self.submodules += lfps_receiver
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self.comb += lfps_receiver.idle.eq(rxelecidle)
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self.comb += lfps_receiver.idle.eq(usb3_serdes.rx_idle)
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# LFPS Polling Transmit --------------------------------------------------------------------
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lfps_transmitter = LFPSTransmitter(sys_clk_freq=sys_clk_freq, lfps_clk_freq=25e6)
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self.submodules += lfps_transmitter
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self.comb += [
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If(lfps_transmitter.polling,
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txelecidle.eq(lfps_transmitter.tx_idle),
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gtx.tx_produce_pattern.eq(~lfps_transmitter.tx_idle),
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gtx.tx_pattern.eq(lfps_transmitter.tx_pattern)
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usb3_serdes.tx_idle.eq(lfps_transmitter.tx_idle),
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usb3_serdes.tx_pattern.eq(lfps_transmitter.tx_pattern)
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).Else(
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txelecidle.eq(0),
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gtx.tx_produce_pattern.eq(0)
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usb3_serdes.tx_idle.eq(0)
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)
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]
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@ -233,22 +182,22 @@ class USB3SoC(SoCMini):
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self.comb += fsm.reset.eq(lfps_receiver.polling)
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fsm.act("POLLING-LFPS",
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scrambler.reset.eq(1),
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gtx.rx_align.eq(1),
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usb3_serdes.gtx.rx_align.eq(1),
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lfps_transmitter.polling.eq(1),
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NextValue(ts2_transmitter.send, 0),
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NextState("WAIT-TSEQ"),
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)
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fsm.act("WAIT-TSEQ",
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gtx.rx_align.eq(1),
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usb3_serdes.gtx.rx_align.eq(1),
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lfps_transmitter.polling.eq(1),
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gtx.source.connect(tseq_receiver.sink),
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usb3_serdes.source.connect(tseq_receiver.sink),
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If(tseq_det_sync.o,
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NextState("SEND-POLLING-LFPS-WAIT-TS1")
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)
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)
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fsm.act("SEND-POLLING-LFPS-WAIT-TS1",
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gtx.rx_align.eq(0),
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gtx.source.connect(ts1_receiver.sink),
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usb3_serdes.gtx.rx_align.eq(0),
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usb3_serdes.source.connect(ts1_receiver.sink),
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If(ts1_det_sync.o,
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NextValue(ts2_transmitter.send, 1),
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NextState("SEND-TS2-WAIT-TS2")
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@ -256,9 +205,9 @@ class USB3SoC(SoCMini):
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)
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ts2_det = Signal()
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fsm.act("SEND-TS2-WAIT-TS2",
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gtx.rx_align.eq(0),
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gtx.source.connect(ts2_receiver.sink),
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ts2_transmitter.source.connect(gtx.sink),
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usb3_serdes.gtx.rx_align.eq(0),
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usb3_serdes.source.connect(ts2_receiver.sink),
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ts2_transmitter.source.connect(usb3_serdes.sink),
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NextValue(ts2_det, ts2_det | ts2_det_sync.o),
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NextValue(ts2_transmitter.send, 0),
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If(ts2_transmitter.done,
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@ -270,15 +219,15 @@ class USB3SoC(SoCMini):
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)
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)
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fsm.act("READY",
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gtx.rx_align.eq(0),
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usb3_serdes.gtx.rx_align.eq(0),
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scrambler.sink.valid.eq(1),
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scrambler.source.connect(gtx.sink),
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scrambler.source.connect(usb3_serdes.sink),
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)
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# Leds -------------------------------------------------------------------------------------
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self.comb += platform.request("user_led", 0).eq(gtx.tx_ready)
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self.comb += platform.request("user_led", 1).eq(gtx.rx_ready)
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self.comb += platform.request("user_led", 7).eq(rxelecidle)
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self.comb += platform.request("user_led", 0).eq(usb3_serdes.gtx.tx_ready)
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self.comb += platform.request("user_led", 1).eq(usb3_serdes.gtx.rx_ready)
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self.comb += platform.request("user_led", 7).eq(usb3_serdes.rx_idle)
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polling_timer = WaitTimer(int(sys_clk_freq*1e-1))
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self.submodules += polling_timer
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self.comb += [
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@ -304,7 +253,7 @@ class USB3SoC(SoCMini):
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if with_rx_analyzer:
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analyzer_signals = [
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fsm,
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gtx.source,
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usb3_serdes.source,
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tseq_receiver.detected,
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ts1_receiver.detected,
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ts1_receiver.reset,
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@ -322,7 +271,7 @@ class USB3SoC(SoCMini):
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if with_tx_analyzer:
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analyzer_signals = [
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fsm,
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gtx.sink,
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usb3_serdes.sink,
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ts2_transmitter.send,
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ts2_transmitter.done,
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]
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