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pcie_screamer/versa_ecp5: increase sys_clk_freq to 150MHz

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This commit is contained in:
Florent Kermarrec 2019-11-13 10:47:33 +01:00
parent f21faf75de
commit a1771ad196
2 changed files with 2 additions and 2 deletions
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2
pcie_screamer.py
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@ -86,7 +86,7 @@ class _CRG(Module):
class USB3SoC(SoCMini):
def __init__(self, platform, with_analyzer=False):
sys_clk_freq = int(133e6)
sys_clk_freq = int(150e6)
SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True)
# CRG --------------------------------------------------------------------------------------

2
versa_ecp5.py
View File

@ -76,7 +76,7 @@ class _CRG(Module):
class USB3SoC(SoCMini):
def __init__(self, platform, connector="pcie", with_etherbone=True, with_analyzer=True):
sys_clk_freq = int(133e6)
sys_clk_freq = int(150e6)
SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True)
# CRG --------------------------------------------------------------------------------------