mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
pocs/kc705: add TS2 Receiver/Transmitter and hacky FSM to try to do the initialization
This commit is contained in:
Florent Kermarrec
parent
e4ffdaf9fc
commit
a1eb6c73ab
@ -2,6 +2,7 @@
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from migen import *
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from migen.genlib.misc import WaitTimer
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from litex.build.generic_platform import *
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@ -19,10 +20,10 @@ from litex.boards.platforms import kc705
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from litescope import LiteScopeAnalyzer
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from usb3_pipe.common import TSEQ, TS1
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from usb3_pipe.common import TSEQ, TS1, TS2
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from usb3_pipe.gtx_7series import GTXChannelPLL, GTX
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from usb3_pipe.lfps import LFPSReceiver, LFPSTransmitter
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from usb3_pipe.ordered_set import OrderedSetReceiver
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from usb3_pipe.ordered_set import OrderedSetReceiver, OrderedSetTransmitter
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# USB3 IOs -----------------------------------------------------------------------------------------
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@ -59,7 +60,9 @@ class USB3SoC(SoCMini):
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def __init__(self, platform,
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with_etherbone=True, mac_address=0x10e2d5000000, ip_address="192.168.1.50",
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with_lfps_analyzer=False,
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with_rx_analyzer=True):
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with_rx_analyzer=True,
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with_tx_analyzer=True,
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with_fsm_analyzer=True):
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sys_clk_freq = int(156.5e6)
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SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True)
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@ -161,23 +164,88 @@ class USB3SoC(SoCMini):
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lfps_transmitter = LFPSTransmitter(sys_clk_freq=sys_clk_freq, lfps_clk_freq=25e6)
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self.submodules += lfps_transmitter
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self.comb += [
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lfps_transmitter.polling.eq(1), # Always generate Polling LFPS for now to receive TSEQ/TS1
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txelecidle.eq(lfps_transmitter.tx_idle),
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gtx.tx_produce_pattern.eq(~lfps_transmitter.tx_idle),
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gtx.tx_pattern.eq(lfps_transmitter.tx_pattern),
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If(lfps_transmitter.polling,
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txelecidle.eq(lfps_transmitter.tx_idle),
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gtx.tx_produce_pattern.eq(~lfps_transmitter.tx_idle),
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gtx.tx_pattern.eq(lfps_transmitter.tx_pattern)
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).Else(
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txelecidle.eq(0),
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gtx.tx_produce_pattern.eq(0)
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)
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]
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# TSEQ Receiver ----------------------------------------------------------------------------
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tseq_receiver = OrderedSetReceiver(ordered_set=TSEQ, n_ordered_sets=1024, data_width=32)
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tseq_receiver = ClockDomainsRenamer("rx")(tseq_receiver)
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self.submodules += tseq_receiver
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self.comb += gtx.source.connect(tseq_receiver.sink)
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# TS1 Receiver ----------------------------------------------------------------------------
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ts1_receiver = OrderedSetReceiver(ordered_set=TS1, n_ordered_sets=1, data_width=32)
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# TS1 Receiver -----------------------------------------------------------------------------
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ts1_receiver = OrderedSetReceiver(ordered_set=TS1, n_ordered_sets=16, data_width=32)
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ts1_receiver = ClockDomainsRenamer("rx")(ts1_receiver)
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self.submodules += ts1_receiver
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self.comb += gtx.source.connect(ts1_receiver.sink)
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# TS2 Receiver -----------------------------------------------------------------------------
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ts2_receiver = OrderedSetReceiver(ordered_set=TS2, n_ordered_sets=1024, data_width=32)
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ts2_receiver = ClockDomainsRenamer("rx")(ts2_receiver)
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self.submodules += ts2_receiver
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# TS2 Transmitter --------------------------------------------------------------------------
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ts2_transmitter = OrderedSetTransmitter(ordered_set=TS2, n_ordered_sets=32768, data_width=32)
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ts2_transmitter = ClockDomainsRenamer("tx")(ts2_transmitter)
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self.submodules += ts2_transmitter
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# Hacky Startup FSM (just to experiment on hardware) ---------------------------------------
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tseq_det_sync = PulseSynchronizer("rx", "sys")
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ts1_det_sync = PulseSynchronizer("rx", "sys")
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ts2_det_sync = PulseSynchronizer("rx", "sys")
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ts2_send_sync = PulseSynchronizer("sys", "tx")
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ts2_done = Signal()
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self.submodules += tseq_det_sync, ts1_det_sync, ts2_det_sync, ts2_send_sync
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self.comb += [
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tseq_det_sync.i.eq(tseq_receiver.detected),
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ts1_det_sync.i.eq(ts1_receiver.detected),
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ts2_det_sync.i.eq(ts2_receiver.detected),
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ts2_transmitter.send.eq(ts2_send_sync.o),
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]
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self.specials += MultiReg(ts2_transmitter.done, ts2_done)
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fsm = FSM(reset_state="POLLING-LFPS")
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fsm = ResetInserter()(fsm)
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self.submodules += fsm
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self.comb += fsm.reset.eq(lfps_receiver.polling)
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fsm.act("POLLING-LFPS",
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gtx.rx_align.eq(1),
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lfps_transmitter.polling.eq(1),
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NextState("WAIT-TSEQ"),
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)
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fsm.act("WAIT-TSEQ",
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gtx.rx_align.eq(1),
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lfps_transmitter.polling.eq(1),
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gtx.source.connect(tseq_receiver.sink),
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If(tseq_det_sync.o,
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NextState("SEND-POLLING-LFPS-WAIT-TS1")
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)
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)
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fsm.act("SEND-POLLING-LFPS-WAIT-TS1",
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gtx.rx_align.eq(0),
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gtx.source.connect(ts1_receiver.sink),
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If(ts1_det_sync.o,
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ts2_send_sync.i.eq(1),
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NextState("SEND-TS2-WAIT-TS2")
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)
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)
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fsm.act("SEND-TS2-WAIT-TS2",
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gtx.rx_align.eq(0),
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gtx.source.connect(ts2_receiver.sink),
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ts2_transmitter.source.connect(gtx.sink),
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If(ts2_done & ts2_det_sync.o,
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NextState("READY")
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)
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)
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fsm.act("READY",
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gtx.rx_align.eq(0)
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)
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# Leds -------------------------------------------------------------------------------------
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self.comb += platform.request("user_led", 0).eq(gtx.tx_ready)
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@ -204,19 +272,44 @@ class USB3SoC(SoCMini):
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self.submodules.lfps_analyzer = LiteScopeAnalyzer(analyzer_signals, 32768, clock_domain="sys", csr_csv="lfps_analyzer.csv")
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self.add_csr("lfps_analyzer")
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# RX Analyzer ---------------------------------------------------------------------------------
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# RX Analyzer ------------------------------------------------------------------------------
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if with_rx_analyzer:
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analyzer_signals = [
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fsm,
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gtx.source,
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tseq_receiver.detected,
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ts1_receiver.detected,
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ts1_receiver.reset,
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ts1_receiver.loopback,
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ts1_receiver.scrambling,
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ts1_receiver.scrambling
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]
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self.submodules.rx_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="rx", csr_csv="rx_analyzer.csv")
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self.add_csr("rx_analyzer")
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# TX Analyzer ------------------------------------------------------------------------------
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if with_tx_analyzer:
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analyzer_signals = [
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fsm,
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gtx.sink,
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ts2_transmitter.send,
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ts2_transmitter.done,
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]
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self.submodules.tx_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="tx", csr_csv="tx_analyzer.csv")
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self.add_csr("tx_analyzer")
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# FSM Analyzer -----------------------------------------------------------------------------
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if with_fsm_analyzer:
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analyzer_signals = [
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fsm,
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tseq_det_sync.o,
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ts1_det_sync.o,
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ts2_det_sync.o,
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ts2_send_sync.i,
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ts2_done
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]
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self.submodules.fsm_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="sys", csr_csv="fsm_analyzer.csv")
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self.add_csr("fsm_analyzer")
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# Build --------------------------------------------------------------------------------------------
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def main():
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43
pocs/kc705/test_fsm_analyzer.py
Executable file
43
pocs/kc705/test_fsm_analyzer.py
Executable file
@ -0,0 +1,43 @@
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#!/usr/bin/env python3
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import sys
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import time
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from litex import RemoteClient
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from litescope import LiteScopeAnalyzerDriver
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wb = RemoteClient()
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wb.open()
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# # #
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# FPGA ID ------------------------------------------------------------------------------------------
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fpga_id = ""
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for i in range(256):
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c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
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fpga_id += c
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if c == "\0":
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break
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print("FPGA: " + fpga_id)
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# Enable Capture -----------------------------------------------------------------------------------
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wb.regs.gtx_rx_polarity.write(1)
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wb.regs.gtx_tx_enable.write(1)
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while (wb.regs.gtx_tx_ready.read() == 0):
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pass
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wb.regs.gtx_rx_enable.write(1)
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while (wb.regs.gtx_rx_ready.read() == 0):
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pass
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# Analyzer dump ------------------------------------------------------------------------------------
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analyzer = LiteScopeAnalyzerDriver(wb.regs, "fsm_analyzer", debug=True)
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analyzer.configure_subsampler(1)
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analyzer.configure_trigger(cond={"soc_ts2_det_sync_o": 0b1})
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analyzer.run(offset=32, length=4096)
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analyzer.wait_done()
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analyzer.upload()
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analyzer.save("analyzer.vcd")
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# # #
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wb.close()
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@ -38,9 +38,9 @@ while (wb.regs.gtx_rx_ready.read() == 0):
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# Analyzer dump ------------------------------------------------------------------------------------
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analyzer = LiteScopeAnalyzerDriver(wb.regs, "rx_analyzer", debug=True)
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analyzer.configure_subsampler(1)
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analyzer.configure_trigger(cond={
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"soc_gtx0_source_payload_ctrl": 0b0001,
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"soc_gtx0_source_payload_data": TSEQ_FIRST_WORD})
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#analyzer.configure_trigger(cond={
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# "soc_gtx0_source_payload_ctrl": 0b0001,
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# "soc_gtx0_source_payload_data": TSEQ_FIRST_WORD})
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analyzer.configure_trigger(cond={
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"soc_gtx0_source_payload_ctrl": 0b1111,
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"soc_gtx0_source_payload_data": TS1_FIRST_WORD})
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46
pocs/kc705/test_tx_analyzer.py
Normal file
46
pocs/kc705/test_tx_analyzer.py
Normal file
@ -0,0 +1,46 @@
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#!/usr/bin/env python3
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import sys
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import time
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from litex import RemoteClient
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from litescope import LiteScopeAnalyzerDriver
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from usb3_pipe.common import TSEQ, TS1
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wb = RemoteClient()
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wb.open()
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# # #
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# FPGA ID ------------------------------------------------------------------------------------------
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fpga_id = ""
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for i in range(256):
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c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
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fpga_id += c
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if c == "\0":
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break
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print("FPGA: " + fpga_id)
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# Enable Capture -----------------------------------------------------------------------------------
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wb.regs.gtx_rx_polarity.write(1)
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wb.regs.gtx_tx_polarity.write(1)
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wb.regs.gtx_tx_enable.write(1)
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while (wb.regs.gtx_tx_ready.read() == 0):
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pass
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wb.regs.gtx_rx_enable.write(1)
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while (wb.regs.gtx_rx_ready.read() == 0):
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pass
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# Analyzer dump ------------------------------------------------------------------------------------
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analyzer = LiteScopeAnalyzerDriver(wb.regs, "tx_analyzer", debug=True)
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analyzer.configure_subsampler(1)
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analyzer.configure_trigger(cond={"soc_gtx0_sink_valid": 1})
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analyzer.run(offset=32, length=4096)
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analyzer.wait_done()
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analyzer.upload()
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analyzer.save("analyzer.vcd")
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# # #
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wb.close()
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