versa_ecp5/CRG: add power on reset

versa_ecp5.py

@@ -56,6 +56,7 @@ _usb3_io = [
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
         self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_por = ClockDomain(reset_less=True)
 
         # # #
 
@@ -63,13 +64,21 @@ class _CRG(Module):
 
         # clk / rst
         clk100 = platform.request("clk100")
+        rst_n  = platform.request("rst_n")
         platform.add_period_constraint(clk100, 1e9/100e6)
 
+        # power on reset
+        por_count = Signal(16, reset=2**16-1)
+        por_done = Signal()
+        self.comb += self.cd_por.clk.eq(ClockSignal())
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
         # pll
         self.submodules.pll = pll = ECP5PLL()
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
-
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
 
 # USB3SoC ------------------------------------------------------------------------------------------
 
@@ -125,7 +134,7 @@ class USB3SoC(SoCMini):
         # USB3 PIPE --------------------------------------------------------------------------------
         usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq, with_scrambling=False)
         self.submodules += usb3_pipe
-        self.comb += usb3_pipe.reset.eq(~platform.request("rst_n"))
+        #self.comb += usb3_pipe.reset.eq(~platform.request("rst_n"))
         self.comb += usb3_pipe.sink.valid.eq(1)
         self.comb += usb3_pipe.source.ready.eq(1)
 
@@ -197,6 +206,7 @@ jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
 """)
     f.close()
     os.system("openocd -f ecp5-versa5g.cfg -c \"transport select jtag; init; svf build/gateware/top.svf; exit\"")
+    exit()
 
 # Build --------------------------------------------------------------------------------------------