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kc705/pcie_screamer: integrate USB3 Core (untested but able P&R successful)

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This commit is contained in:
Florent Kermarrec 2019-11-22 12:59:50 +01:00
parent 480490a48e
commit aa1b01ca22
2 changed files with 25 additions and 7 deletions
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15
kc705.py
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@ -24,6 +24,7 @@ from liteeth.frontend.etherbone import LiteEthEtherbone
from litescope import LiteScopeAnalyzer
from usb3_pipe import K7USB3SerDes, USB3PIPE
from usb3_core.core import USB3Core
# USB3 IOs -----------------------------------------------------------------------------------------
@ -116,10 +117,18 @@ class USB3SoC(SoCMini):
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += usb3_pipe
self.submodules.usb3_pipe = usb3_pipe
self.comb += usb3_pipe.reset.eq(platform.request("cpu_reset"))
self.comb += usb3_pipe.sink.valid.eq(1)
self.comb += usb3_pipe.source.ready.eq(1)
# USB3 Core --------------------------------------------------------------------------------
usb3_core = USB3Core(platform)
self.submodules.usb3_core = usb3_core
self.comb += [
usb3_pipe.source.connect(usb3_core.sink),
usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready),
]
self.add_csr("usb3_core")
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)

17
pcie_screamer.py
View File

@ -21,6 +21,7 @@ from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer
from usb3_pipe import A7USB3SerDes, USB3PIPE
from usb3_core.core import USB3Core
# IOs ----------------------------------------------------------------------------------------------
@ -107,12 +108,20 @@ class USB3SoC(SoCMini):
self.submodules += usb3_serdes
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# USB3 PHY ---------------------------------------------------------------------------------
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += usb3_pipe
self.submodules.usb3_pipe = usb3_pipe
self.comb += usb3_pipe.reset.eq(~platform.request("user_btn", 0))
self.comb += usb3_pipe.sink.valid.eq(1)
self.comb += usb3_pipe.source.ready.eq(1)
# USB3 Core --------------------------------------------------------------------------------
usb3_core = USB3Core(platform)
self.submodules.usb3_core = usb3_core
self.comb += [
usb3_pipe.source.connect(usb3_core.sink),
usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready),
]
self.add_csr("usb3_core")
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)