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https://github.com/enjoy-digital/usb3_pipe.git
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serdes/Datapath: add phy_dw parameter
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commit
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@ -214,9 +214,9 @@ class TXSkipInserter(Module):
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# Datapath (Clock Domain Crossing & Converter) -----------------------------------------------------
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class SerdesTXDatapath(Module):
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def __init__(self, clock_domain="sys"):
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def __init__(self, clock_domain="sys", phy_dw=16):
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self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
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self.source = stream.Endpoint([("data", 16), ("ctrl", 2)])
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self.source = stream.Endpoint([("data", phy_dw), ("ctrl", phy_dw//8)])
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# # #
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@ -227,7 +227,7 @@ class SerdesTXDatapath(Module):
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self.submodules.cdc = cdc
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converter = stream.StrideConverter(
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[("data", 32), ("ctrl", 4)],
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[("data", 16), ("ctrl", 2)],
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[("data", phy_dw), ("ctrl", phy_dw//8)],
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reverse=False)
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converter = stream.BufferizeEndpoints({"source": stream.DIR_SOURCE})(converter)
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converter = ClockDomainsRenamer(clock_domain)(converter)
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@ -240,14 +240,14 @@ class SerdesTXDatapath(Module):
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]
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class SerdesRXDatapath(Module):
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def __init__(self, clock_domain="sys"):
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self.sink = stream.Endpoint([("data", 16), ("ctrl", 2)])
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def __init__(self, clock_domain="sys", phy_dw=16):
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self.sink = stream.Endpoint([("data", phy_dw), ("ctrl", phy_dw//8)])
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self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
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# # #
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converter = stream.StrideConverter(
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[("data", 16), ("ctrl", 2)],
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[("data", phy_dw), ("ctrl", phy_dw//8)],
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[("data", 32), ("ctrl", 4)],
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reverse=False)
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converter = stream.BufferizeEndpoints({"sink": stream.DIR_SINK})(converter)
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