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targets: set polarity and use a common analyzer

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This commit is contained in:
Florent Kermarrec 2019-10-08 11:29:39 +02:00
parent 362fe4f444
commit b138f0fc2e
6 changed files with 113 additions and 152 deletions
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24
kc705.py
View File

@ -68,7 +68,7 @@ class _CRG(Module):
class USB3SoC(SoCMini):
def __init__(self, platform, connector="usb3",
with_etherbone=True, mac_address=0x10e2d5000000, ip_address="192.168.1.50",
with_analyzer=False):
with_analyzer=True):
sys_clk_freq = int(156.5e6)
SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True)
@ -115,6 +115,10 @@ class USB3SoC(SoCMini):
tx_pads = platform.request(connector + "_tx"),
rx_pads = platform.request(connector + "_rx"))
self.submodules += usb3_serdes
self.comb += [
usb3_serdes.tx_polarity.eq(1 if connector == "usb3" else 0),
usb3_serdes.rx_polarity.eq(1 if connector == "usb3" else 0),
]
# USB3 PHY ---------------------------------------------------------------------------------
usb3_phy = USB3PHY(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
@ -127,9 +131,25 @@ class USB3SoC(SoCMini):
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# LFPS
usb3_serdes.tx_idle,
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_phy.lfps.rx_polling,
usb3_phy.lfps.tx_polling,
# Training Sequence
usb3_phy.ts.rx_tseq,
usb3_phy.ts.rx_ts1,
usb3_phy.ts.rx_ts2,
usb3_phy.ts.tx_ts2,
# LTSSM
usb3_phy.ltssm.polling_fsm,
# Endpoints
usb3_serdes.source,
usb3_serdes.sink,
usb3_phy.ltssm.polling_fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")

22
pcie_screamer.py
View File

@ -101,6 +101,10 @@ class USB3SoC(SoCMini):
tx_pads = platform.request("pcie_tx"),
rx_pads = platform.request("pcie_rx"))
self.submodules += usb3_serdes
self.comb += [
usb3_serdes.tx_polarity.eq(0),
usb3_serdes.rx_polarity.eq(0),
]
# USB3 PHY ---------------------------------------------------------------------------------
usb3_phy = USB3PHY(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
@ -113,9 +117,25 @@ class USB3SoC(SoCMini):
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# LFPS
usb3_serdes.tx_idle,
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_phy.lfps.rx_polling,
usb3_phy.lfps.tx_polling,
# Training Sequence
usb3_phy.ts.rx_tseq,
usb3_phy.ts.rx_ts1,
usb3_phy.ts.rx_ts2,
usb3_phy.ts.tx_ts2,
# LTSSM
usb3_phy.ltssm.polling_fsm,
# Endpoints
usb3_serdes.source,
usb3_serdes.sink,
usb3_phy.ltssm.polling_fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")

70
tools/test_analyzer.py Executable file
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@ -0,0 +1,70 @@
#!/usr/bin/env python3
import sys
import time
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
def help():
print("Supported triggers:")
print(" - rx_polling")
print(" - tx_polling")
print("")
print(" - rx_tseq")
print(" - rx_ts1")
print(" - rx_ts2")
print(" - tx_ts2")
print("")
print(" - now")
exit()
if len(sys.argv) < 2:
help()
if len(sys.argv) < 3:
length = 4096
else:
length = int(sys.argv[2])
# FPGA ID ------------------------------------------------------------------------------------------
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
fpga_id += c
if c == "\0":
break
print("FPGA: " + fpga_id)
# Analyzer dump ------------------------------------------------------------------------------------
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
if sys.argv[1] == "rx_polling":
analyzer.configure_trigger(cond={"soc_usb3_phy_lfps_rx_polling" : 1})
elif sys.argv[1] == "tx_polling":
analyzer.configure_trigger(cond={"soc_usb3_phy_lfps_tx_polling" : 1})
elif sys.argv[1] == "rx_tseq":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_rx_tseq" : 1})
elif sys.argv[1] == "rx_ts1":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_rx_ts1" : 1})
elif sys.argv[1] == "rx_ts2":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_rx_ts2" : 1})
elif sys.argv[1] == "tx_ts2":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_tx_ts2" : 1})
elif sys.argv[1] == "now":
analyzer.configure_trigger(cond={})
else:
raise ValueError
analyzer.configure_trigger(cond={})
analyzer.run(offset=32, length=length)
analyzer.wait_done()
analyzer.upload()
analyzer.save("analyzer.vcd")
# # #
wb.close()

45
tools/test_lfps_analyzer.py
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@ -1,45 +0,0 @@
#!/usr/bin/env python3
import sys
import time
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
# FPGA ID ------------------------------------------------------------------------------------------
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
fpga_id += c
if c == "\0":
break
print("FPGA: " + fpga_id)
# Enable Capture -----------------------------------------------------------------------------------
wb.regs.gtx_rx_polarity.write(0)
wb.regs.gtx_tx_enable.write(1)
while (wb.regs.gtx_tx_ready.read() == 0):
pass
wb.regs.gtx_rx_enable.write(1)
while (wb.regs.gtx_rx_ready.read() == 0):
pass
# Analyzer dump ------------------------------------------------------------------------------------
analyzer = LiteScopeAnalyzerDriver(wb.regs, "lfps_analyzer", debug=True)
analyzer.configure_subsampler(1)
analyzer.configure_trigger(cond={"soc_lfps_receiver_polling": 1})
#analyzer.configure_trigger(cond={"soc_rxelecidle": 0})
#analyzer.configure_trigger(cond={})
analyzer.run(offset=8192, length=32468)
analyzer.wait_done()
analyzer.upload()
analyzer.save("analyzer.vcd")
# # #
wb.close()

57
tools/test_rx_analyzer.py
View File

@ -1,57 +0,0 @@
#!/usr/bin/env python3
import sys
import time
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
from usb3_pipe.common import TSEQ, TS1, TS2
wb = RemoteClient()
wb.open()
# # #
TSEQ_FIRST_WORD = int.from_bytes(TSEQ.to_bytes()[0:4], byteorder="little")
TS1_FIRST_WORD = int.from_bytes(TS1.to_bytes()[0:4], byteorder="little")
# FPGA ID ------------------------------------------------------------------------------------------
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
fpga_id += c
if c == "\0":
break
print("FPGA: " + fpga_id)
# Enable Capture -----------------------------------------------------------------------------------
wb.regs.gtx_rx_polarity.write(1)
wb.regs.gtx_tx_enable.write(1)
while (wb.regs.gtx_tx_ready.read() == 0):
pass
wb.regs.gtx_rx_enable.write(1)
while (wb.regs.gtx_rx_ready.read() == 0):
pass
# Analyzer dump ------------------------------------------------------------------------------------
analyzer = LiteScopeAnalyzerDriver(wb.regs, "rx_analyzer", debug=True)
analyzer.configure_subsampler(1)
#analyzer.configure_trigger(cond={
# "soc_gtx0_source_payload_ctrl": 0b0001,
# "soc_gtx0_source_payload_data": TSEQ_FIRST_WORD})
#analyzer.configure_trigger(cond={
# "soc_gtx0_source_payload_ctrl": 0b1111,
# "soc_gtx0_source_payload_data": TS1_FIRST_WORD})
#analyzer.configure_trigger(cond={"soc_tseq_receiver_detected": 1})
#analyzer.configure_trigger(cond={"soc_ts1_receiver_detected": 1})
#analyzer.configure_trigger(cond={"soc_ts2_receiver_detected": 1})
analyzer.configure_trigger(cond={})
analyzer.run(offset=32, length=4096)
analyzer.wait_done()
analyzer.upload()
analyzer.save("analyzer.vcd")
# # #
wb.close()

47
tools/test_tx_analyzer.py
View File

@ -1,47 +0,0 @@
#!/usr/bin/env python3
import sys
import time
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
from usb3_pipe.common import TSEQ, TS1
wb = RemoteClient()
wb.open()
# # #
# FPGA ID ------------------------------------------------------------------------------------------
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
fpga_id += c
if c == "\0":
break
print("FPGA: " + fpga_id)
# Enable Capture -----------------------------------------------------------------------------------
wb.regs.gtx_rx_polarity.write(1)
wb.regs.gtx_tx_polarity.write(1)
wb.regs.gtx_tx_enable.write(1)
while (wb.regs.gtx_tx_ready.read() == 0):
pass
wb.regs.gtx_rx_enable.write(1)
while (wb.regs.gtx_rx_ready.read() == 0):
pass
# Analyzer dump ------------------------------------------------------------------------------------
analyzer = LiteScopeAnalyzerDriver(wb.regs, "tx_analyzer", debug=True)
analyzer.configure_subsampler(1)
analyzer.configure_trigger(cond={"soc_gtx0_sink_valid": 1})
analyzer.configure_trigger(cond={})
analyzer.run(offset=32, length=4096)
analyzer.wait_done()
analyzer.upload()
analyzer.save("analyzer.vcd")
# # #
wb.close()