FPGA/usb3_pipe
1
0
Fork 0
mirror of https://github.com/enjoy-digital/usb3_pipe.git synced 2025-01-04 10:18:41 +08:00
Code Issues Projects Releases Wiki Activity

usb3_core/core: document

Browse Source
This commit is contained in:
Florent Kermarrec 2019-12-13 15:04:03 +01:00
parent 445d8d183c
commit b42b25fb47
1 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
usb3_core/core.py
View File

@ -51,6 +51,15 @@ class USB3CoreEndpoint(Module, AutoCSR):
# USB3 Core ----------------------------------------------------------------------------------------
class USB3Core(Module, AutoCSR):
"""USB3.0 Core
Wrap the Daisho USB3.0 Core (https://github.com/mossmann/daisho) in a Module with small adaptations
to make it compatible with the USB3.0 PIPE.
- New top to only keep link/protocol layers and and endpoints.
- Additional logic to emulate Daisho's internal ltssm states.
- Additional RX words alignment. FIXME: could we avoid it or do it or should we do it in the PIPE?
- Additional TX FIFO to handle back-pressure from the SerDes. (not handled by Daisho)
"""
def __init__(self, platform, with_endpoint=False):
self.reset = Signal()
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
@ -169,6 +178,7 @@ class USB3Core(Module, AutoCSR):
# Daisho USB3 instance ---------------------------------------------------------------------
self.specials += Instance("usb3_top_usb3_pipe", **usb3_top_params)
# Daisho USB3 sources ----------------------------------------------------------------------
daisho_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "daisho")
platform.add_verilog_include_path(os.path.join(daisho_path))
platform.add_verilog_include_path(os.path.join(daisho_path, "usb3"))