From b46f0108e476116c0761ea2defc8600fea94f0d7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 7 Oct 2019 22:36:04 +0200 Subject: [PATCH] ordered_set: only keep 32-bit data-width --- test/test_ordered_set.py | 8 +++--- usb3_pipe/ordered_set.py | 57 ++++++++++++++-------------------------- 2 files changed, 24 insertions(+), 41 deletions(-) diff --git a/test/test_ordered_set.py b/test/test_ordered_set.py index 91707dd..d1f4d20 100644 --- a/test/test_ordered_set.py +++ b/test/test_ordered_set.py @@ -32,7 +32,7 @@ class TestOrderedSet(unittest.TestCase): yield self.assertEqual(count, n_loops/n_ordered_sets) - dut = OrderedSetChecker(ordered_set=TSEQ, n_ordered_sets=4, data_width=32) + dut = OrderedSetChecker(ordered_set=TSEQ, n_ordered_sets=4) dut.run = True generators = [ generator(dut, n_loops=32), @@ -66,7 +66,7 @@ class TestOrderedSet(unittest.TestCase): yield self.assertEqual(count, n_loops/n_ordered_sets) - dut = OrderedSetChecker(ordered_set=TS1, n_ordered_sets=4, data_width=32) + dut = OrderedSetChecker(ordered_set=TS1, n_ordered_sets=4) dut.run = True generators = [ generator(dut, n_loops=32), @@ -100,7 +100,7 @@ class TestOrderedSet(unittest.TestCase): yield self.assertEqual(words, tseq_words*n_loops*n_ordered_sets) - dut = OrderedSetGenerator(ordered_set=TSEQ, n_ordered_sets=4, data_width=32) + dut = OrderedSetGenerator(ordered_set=TSEQ, n_ordered_sets=4) dut.run = True generators = [ generator(dut, n_loops=32), @@ -137,7 +137,7 @@ class TestOrderedSet(unittest.TestCase): yield self.assertEqual(words, ts1_words*n_loops*n_ordered_sets) - dut = OrderedSetGenerator(ordered_set=TS1, n_ordered_sets=4, data_width=32) + dut = OrderedSetGenerator(ordered_set=TS1, n_ordered_sets=4) dut.run = True generators = [ generator(dut, n_loops=32), diff --git a/usb3_pipe/ordered_set.py b/usb3_pipe/ordered_set.py index 17e0706..06d9cf3 100644 --- a/usb3_pipe/ordered_set.py +++ b/usb3_pipe/ordered_set.py @@ -10,9 +10,8 @@ from usb3_pipe.common import TSEQ, TS1, TS2 # Ordered Set Checker ------------------------------------------------------------------------------ class OrderedSetChecker(Module): - def __init__(self, ordered_set, n_ordered_sets, data_width): - assert data_width in [16, 32] - self.sink = stream.Endpoint([("data", data_width), ("ctrl", data_width//8)]) + def __init__(self, ordered_set, n_ordered_sets): + self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)]) self.detected = Signal() # o if ordered_set.name in ["TS1", "TS2"]: @@ -25,21 +24,18 @@ class OrderedSetChecker(Module): self.comb += self.sink.ready.eq(1) # Memory -------------------------------------------------------------------------------- - mem_depth = len(ordered_set.to_bytes())//(data_width//8) + mem_depth = len(ordered_set.to_bytes())//4 mem_init = [int.from_bytes(ordered_set.to_bytes()[4*i:4*(i+1)], "little") for i in range(mem_depth)] - mem = Memory(data_width, mem_depth, mem_init) + mem = Memory(32, mem_depth, mem_init) port = mem.get_port(async_read=True) self.specials += mem, port # Data check ------------------------------------------------------------------------------- error = Signal() - error_mask = Signal(data_width, reset=2**data_width-1) + error_mask = Signal(32, reset=2**32-1) if ordered_set.name in ["TS1", "TS2"]: - first_ctrl = 2**(data_width//8) - 1 - if data_width == 32: - self.comb += If(port.adr == 1, error_mask.eq(0xffff00ff)) - else: - self.comb += If(port.adr == 2, error_mask.eq(0x00ff)) + first_ctrl = 2**4 - 1 + self.comb += If(port.adr == 1, error_mask.eq(0xffff00ff)) else: first_ctrl = 1 self.comb += [ @@ -60,22 +56,13 @@ class OrderedSetChecker(Module): # Link Config ------------------------------------------------------------------------------ if ordered_set.name in ["TS1", "TS2"]: - if data_width == 32: - self.sync += [ - If(self.sink.valid & (port.adr == 1), - self.reset.eq( self.sink.data[ 8]), - self.loopback.eq( self.sink.data[10]), - self.scrambling.eq(~self.sink.data[11]) - ) - ] - else: - self.sync += [ - If(self.sink.valid & (port.adr == 2), - self.reset.eq( self.sink.data[ 8]), - self.loopback.eq( self.sink.data[10]), - self.scrambling.eq(~self.sink.data[11]) - ) - ] + self.sync += [ + If(self.sink.valid & (port.adr == 1), + self.reset.eq( self.sink.data[ 8]), + self.loopback.eq( self.sink.data[10]), + self.scrambling.eq(~self.sink.data[11]) + ) + ] # Memory address generation ---------------------------------------------------------------- self.sync += [ @@ -110,11 +97,10 @@ class OrderedSetChecker(Module): # Ordered Set Generator ---------------------------------------------------------------------------- class OrderedSetGenerator(Module): - def __init__(self, ordered_set, n_ordered_sets, data_width): - assert data_width in [16, 32] + def __init__(self, ordered_set, n_ordered_sets): self.send = Signal() # i self.done = Signal() # i - self.source = stream.Endpoint([("data", data_width), ("ctrl", data_width//8)]) + self.source = stream.Endpoint([("data", 32), ("ctrl", 4)]) if ordered_set.name in ["TS1", "TS2"]: self.reset = Signal() # i @@ -126,9 +112,9 @@ class OrderedSetGenerator(Module): run = Signal() # Memory -------------------------------------------------------------------------------- - mem_depth = len(ordered_set.to_bytes())//(data_width//8) + mem_depth = len(ordered_set.to_bytes())//4 mem_init = [int.from_bytes(ordered_set.to_bytes()[4*i:4*(i+1)], "little") for i in range(mem_depth)] - mem = Memory(data_width, mem_depth, mem_init) + mem = Memory(32, mem_depth, mem_init) port = mem.get_port(async_read=True) self.specials += mem, port @@ -156,7 +142,7 @@ class OrderedSetGenerator(Module): # Data generation -------------------------------------------------------------------------- if ordered_set.name in ["TS1", "TS2"]: - first_ctrl = 2**(data_width//8) - 1 + first_ctrl = 2**4 - 1 else: first_ctrl = 1 self.comb += [ @@ -169,10 +155,7 @@ class OrderedSetGenerator(Module): self.source.data.eq(port.dat_r) ] if ordered_set.name in ["TS1", "TS2"]: - if data_width == 32: - self.comb += If(port.adr == 1, self.source.data[8:16].eq(link_config)) - else: - self.comb += If(port.adr == 2, self.source.data[8:16].eq(link_config)) + self.comb += If(port.adr == 1, self.source.data[8:16].eq(link_config)) # Count ------------------------------------------------------------------------------------ count = Signal(max=mem_depth*n_ordered_sets)