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usb3_pipe/serdes: add rx_align, regroup tx/rx controls signals

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This commit is contained in:
Florent Kermarrec 2019-10-07 17:07:33 +02:00
parent 9bf8442c9d
commit ba2e8dc770
2 changed files with 11 additions and 8 deletions
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10
kc705.py
View File

@ -182,13 +182,13 @@ class USB3SoC(SoCMini):
self.comb += fsm.reset.eq(lfps_receiver.polling)
fsm.act("POLLING-LFPS",
scrambler.reset.eq(1),
usb3_serdes.gtx.rx_align.eq(1),
usb3_serdes.rx_align.eq(1),
lfps_transmitter.polling.eq(1),
NextValue(ts2_transmitter.send, 0),
NextState("WAIT-TSEQ"),
)
fsm.act("WAIT-TSEQ",
usb3_serdes.gtx.rx_align.eq(1),
usb3_serdes.rx_align.eq(1),
lfps_transmitter.polling.eq(1),
usb3_serdes.source.connect(tseq_receiver.sink),
If(tseq_det_sync.o,
@ -196,7 +196,7 @@ class USB3SoC(SoCMini):
)
)
fsm.act("SEND-POLLING-LFPS-WAIT-TS1",
usb3_serdes.gtx.rx_align.eq(0),
usb3_serdes.rx_align.eq(0),
usb3_serdes.source.connect(ts1_receiver.sink),
If(ts1_det_sync.o,
NextValue(ts2_transmitter.send, 1),
@ -205,7 +205,7 @@ class USB3SoC(SoCMini):
)
ts2_det = Signal()
fsm.act("SEND-TS2-WAIT-TS2",
usb3_serdes.gtx.rx_align.eq(0),
usb3_serdes.rx_align.eq(0),
usb3_serdes.source.connect(ts2_receiver.sink),
ts2_transmitter.source.connect(usb3_serdes.sink),
NextValue(ts2_det, ts2_det | ts2_det_sync.o),
@ -219,7 +219,7 @@ class USB3SoC(SoCMini):
)
)
fsm.act("READY",
usb3_serdes.gtx.rx_align.eq(0),
usb3_serdes.rx_align.eq(0),
scrambler.sink.valid.eq(1),
scrambler.source.connect(usb3_serdes.sink),
)

9
usb3_pipe/serdes.py
View File

@ -10,13 +10,15 @@ class K7USB3SerDes(Module):
self.source = stream.Endpoint([("data", 16), ("ctrl", 4)])
self.enable = Signal()
self.tx_polarity = Signal()
self.rx_polarity = Signal()
self.rx_idle = Signal()
self.tx_polarity = Signal()
self.tx_idle = Signal()
self.tx_pattern = Signal(20)
self.rx_polarity = Signal()
self.rx_idle = Signal()
self.rx_align = Signal()
# # #
from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTX
@ -53,6 +55,7 @@ class K7USB3SerDes(Module):
self.comb += [
gtx.tx_enable.eq(self.enable),
gtx.rx_enable.eq(self.enable),
gtx.rx_align.eq(self.rx_align),
self.sink.connect(gtx.sink),
gtx.source.connect(self.source),
]