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rename ordered_set to training

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This commit is contained in:
Florent Kermarrec 2019-10-08 09:06:08 +02:00
parent 68c09044a7
commit bdf61f9e40
5 changed files with 35 additions and 35 deletions
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12
test/test_ordered_set.py → test/test_training.py
View File

@ -6,10 +6,10 @@ import unittest
from migen import *
from usb3_pipe.common import TSEQ, TS1
from usb3_pipe.ordered_set import OrderedSetChecker, OrderedSetGenerator
from usb3_pipe.training import TSChecker, TSGenerator
class TestOrderedSet(unittest.TestCase):
class TestTraining(unittest.TestCase):
def test_tseq_checker(self):
tseq_length = len(TSEQ.to_bytes())//4
tseq_words = [int.from_bytes(TSEQ.to_bytes()[4*i:4*(i+1)], "little") for i in range(tseq_length)]
@ -32,7 +32,7 @@ class TestOrderedSet(unittest.TestCase):
yield
self.assertEqual(count, n_loops/n_ordered_sets)
dut = OrderedSetChecker(ordered_set=TSEQ, n_ordered_sets=4)
dut = TSChecker(ordered_set=TSEQ, n_ordered_sets=4)
dut.run = True
generators = [
generator(dut, n_loops=32),
@ -66,7 +66,7 @@ class TestOrderedSet(unittest.TestCase):
yield
self.assertEqual(count, n_loops/n_ordered_sets)
dut = OrderedSetChecker(ordered_set=TS1, n_ordered_sets=4)
dut = TSChecker(ordered_set=TS1, n_ordered_sets=4)
dut.run = True
generators = [
generator(dut, n_loops=32),
@ -100,7 +100,7 @@ class TestOrderedSet(unittest.TestCase):
yield
self.assertEqual(words, tseq_words*n_loops*n_ordered_sets)
dut = OrderedSetGenerator(ordered_set=TSEQ, n_ordered_sets=4)
dut = TSGenerator(ordered_set=TSEQ, n_ordered_sets=4)
dut.run = True
generators = [
generator(dut, n_loops=32),
@ -137,7 +137,7 @@ class TestOrderedSet(unittest.TestCase):
yield
self.assertEqual(words, ts1_words*n_loops*n_ordered_sets)
dut = OrderedSetGenerator(ordered_set=TS1, n_ordered_sets=4)
dut = TSGenerator(ordered_set=TS1, n_ordered_sets=4)
dut.run = True
generators = [
generator(dut, n_loops=32),

2
usb3_pipe/common.py
View File

@ -36,7 +36,7 @@ EPF = Symbol("EPF", K(23, 7), "End Packet Framing")
symbols = [SKP, SDP, EDB, SUB, COM, RSD, SHP, END, SLC, EPF]
# Ordered Sets -------------------------------------------------------------------------------------
# Training Sequence Ordered Sets -------------------------------------------------------------------
class OrderedSet(list):
def __init__(self, name, values, description=""):

16
usb3_pipe/ltssm.py
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@ -163,7 +163,7 @@ class RXDetectFSM(FSM):
@ResetInserter()
class PollingFSM(FSM):
""" Polling Finite State Machine (section 7.5.4)"""
def __init__(self, lfps_unit, ordered_set_unit):
def __init__(self, lfps_unit, ts_unit):
self.exit_to_compliance_mode = Signal()
self.exit_to_rx_detect = Signal()
self.exit_to_ss_disabled = Signal()
@ -189,7 +189,7 @@ class PollingFSM(FSM):
# RxEQ State -------------------------------------------------------------------------------
self.act("RX-EQ",
If(ordered_set_unit.rx_tseq,
If(ts_unit.rx_tseq,
NextState("ACTIVE"), # TSEQ transmitted.
),
#self.exit_to_ss_disabled.eq(1), # Directed (DS).
@ -198,7 +198,7 @@ class PollingFSM(FSM):
# Active State -----------------------------------------------------------------------------
self.act("ACTIVE",
If(ordered_set_unit.rx_ts1 | ordered_set_unit.rx_ts2,
If(ts_unit.rx_ts1 | ts_unit.rx_ts2,
NextState("CONFIGURATION"), # 8 consecutiive TS1 or TS2 received.
),
#self.exit_to_ss_disabled.eq(1), # Timeout (Dev) or directed (DS).
@ -208,8 +208,8 @@ class PollingFSM(FSM):
# Configuration State ----------------------------------------------------------------------
self.act("CONFIGURATION",
ordered_set_unit.tx_ts2.eq(1),
If(ordered_set_unit.rx_ts2,
ts_unit.tx_ts2.eq(1),
If(ts_unit.rx_ts2,
NextState("IDLE"), # TS2 handshake.
),
#self.exit_to_ss_disabled.eq(1), # Timeout (Dev) or directed (DS).
@ -234,7 +234,7 @@ class PollingFSM(FSM):
# Link Training and Status State Machine -----------------------------------------------------------
class LTSSM(Module):
def __init__(self, lfps_unit, ordered_set_unit):
def __init__(self, lfps_unit, ts_unit):
# SS Inactive FSM --------------------------------------------------------------------------
self.submodules.ss_inactive_fsm = SSInactiveFSM()
@ -243,8 +243,8 @@ class LTSSM(Module):
# Polling FSM ------------------------------------------------------------------------------
self.submodules.polling_fsm = PollingFSM(
lfps_unit = lfps_unit,
ordered_set_unit = ordered_set_unit)
lfps_unit = lfps_unit,
ts_unit = ts_unit)
self.comb += self.polling_fsm.reset.eq(lfps_unit.rx_polling)
# LTSSM FSM --------------------------------------------------------------------------------

16
usb3_pipe/phy.py
View File

@ -6,7 +6,7 @@ from migen import *
from litex.soc.interconnect import stream
from usb3_pipe.lfps import LFPSUnit
from usb3_pipe.ordered_set import OrderedSetUnit
from usb3_pipe.training import TSUnit
from usb3_pipe.ltssm import LTSSM
# USB3 PHY -----------------------------------------------------------------------------------------
@ -22,16 +22,16 @@ class USB3PHY(Module):
# # #
# LFPS Unit --------------------------------------------------------------------------------
lfps_unit = LFPSUnit(sys_clk_freq=sys_clk_freq, serdes=serdes)
self.submodules.lfps_unit = lfps_unit
# LFPS -------------------------------------------------------------------------------------
lfps = LFPSUnit(sys_clk_freq=sys_clk_freq, serdes=serdes)
self.submodules.lfps = lfps
# OrderedSet Unit --------------------------------------------------------------------------
ordered_set_unit = OrderedSetUnit(serdes=serdes)
self.submodules.ordered_set_unit = ordered_set_unit
# TS----------------------------------------------------------------------------------------
ts = TSUnit(serdes=serdes)
self.submodules.ts = ts
# LTSSM ------------------------------------------------------------------------------------
ltssm = LTSSM(lfps_unit=lfps_unit, ordered_set_unit=ordered_set_unit)
ltssm = LTSSM(lfps_unit=lfps, ts_unit=ts)
self.submodules.ltssm = ltssm
self.comb += self.ready.eq(ltssm.polling_fsm.idle)

24
usb3_pipe/ordered_set.py → usb3_pipe/training.py
View File

@ -7,9 +7,9 @@ from litex.soc.interconnect import stream
from usb3_pipe.common import TSEQ, TS1, TS2
# Ordered Set Checker ------------------------------------------------------------------------------
# Training Sequence Checker ------------------------------------------------------------------------
class OrderedSetChecker(Module):
class TSChecker(Module):
def __init__(self, ordered_set, n_ordered_sets):
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.detected = Signal() # o
@ -23,7 +23,7 @@ class OrderedSetChecker(Module):
self.comb += self.sink.ready.eq(1)
# Memory --------------------------------------------------------------------------------
# Memory -----------------------------------------------------------------------------------
mem_depth = len(ordered_set.to_bytes())//4
mem_init = [int.from_bytes(ordered_set.to_bytes()[4*i:4*(i+1)], "little") for i in range(mem_depth)]
mem = Memory(32, mem_depth, mem_init)
@ -94,9 +94,9 @@ class OrderedSetChecker(Module):
# Result -----------------------------------------------------------------------------------
self.comb += self.detected.eq(count == (mem_depth*n_ordered_sets - 1))
# Ordered Set Generator ----------------------------------------------------------------------------
# Training Sequence Generator ----------------------------------------------------------------------
class OrderedSetGenerator(Module):
class TSGenerator(Module):
def __init__(self, ordered_set, n_ordered_sets):
self.send = Signal() # i
self.done = Signal() # i
@ -173,9 +173,9 @@ class OrderedSetGenerator(Module):
# Result -----------------------------------------------------------------------------------
self.comb += self.done.eq(count == (mem_depth*n_ordered_sets - 1))
# Ordered Set Unit ---------------------------------------------------------------------------------
# Training Sequence Unit ---------------------------------------------------------------------------
class OrderedSetUnit(Module):
class TSUnit(Module):
def __init__(self, serdes):
self.rx_tseq = Signal() # o
self.rx_ts1 = Signal() # o
@ -185,9 +185,9 @@ class OrderedSetUnit(Module):
# # #
# Ordered Set Checkers ---------------------------------------------------------------------
tseq_checker = OrderedSetChecker(ordered_set=TSEQ, n_ordered_sets=8)
ts1_checker = OrderedSetChecker(ordered_set=TS1, n_ordered_sets=8)
ts2_checker = OrderedSetChecker(ordered_set=TS2, n_ordered_sets=8)
tseq_checker = TSChecker(ordered_set=TSEQ, n_ordered_sets=8)
ts1_checker = TSChecker(ordered_set=TS1, n_ordered_sets=8)
ts2_checker = TSChecker(ordered_set=TS2, n_ordered_sets=8)
self.submodules += tseq_checker, ts1_checker, ts2_checker
self.comb += [
serdes.source.connect(tseq_checker.sink, omit={"ready"}),
@ -196,11 +196,11 @@ class OrderedSetUnit(Module):
]
# Ordered Set Generators -------------------------------------------------------------------
ts2_generator = OrderedSetGenerator(ordered_set=TS2, n_ordered_sets=8)
ts2_generator = TSGenerator(ordered_set=TS2, n_ordered_sets=8)
self.submodules += ts2_generator
self.comb += [
If(self.tx_ts2,
ts2_generator.send.eq(1),
ts2_generator.source.connect(serdes.sink),
),
)
]