From c39ed5f38cbc8f1648cc049e1144593a90a112a2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 10 Oct 2019 10:35:01 +0200
Subject: [PATCH] core/USB3PIPE: integrate scrambler/descrambler

---
 sim.py                  |  4 ++++
 usb3_pipe/core.py       | 20 ++++++++++++++++++++
 usb3_pipe/scrambling.py |  2 --
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/sim.py b/sim.py
index 010ab59..a6a82a7 100755
--- a/sim.py
+++ b/sim.py
@@ -50,12 +50,16 @@ class USB3PIPESim(SoCMini):
         host_usb3_serdes = USB3SerDesModel()
         host_usb3_pipe   = USB3PIPE(serdes=host_usb3_serdes, sys_clk_freq=sys_clk_freq)
         self.submodules += host_usb3_serdes, host_usb3_pipe
+        self.comb += host_usb3_pipe.sink.valid.eq(1)
+        self.comb += host_usb3_pipe.source.ready.eq(1)
         host_usb3_pipe.finalize()
 
         # USB3 Device
         dev_usb3_serdes = USB3SerDesModel()
         dev_usb3_pipe   = USB3PIPE(serdes=dev_usb3_serdes, sys_clk_freq=sys_clk_freq)
         self.submodules += dev_usb3_serdes, dev_usb3_pipe
+        self.comb += dev_usb3_pipe.sink.valid.eq(1)
+        self.comb += dev_usb3_pipe.source.ready.eq(1)
         dev_usb3_pipe.finalize()
 
         # Connect Host <--> Device
diff --git a/usb3_pipe/core.py b/usb3_pipe/core.py
index bbf8b8f..ec04cc0 100644
--- a/usb3_pipe/core.py
+++ b/usb3_pipe/core.py
@@ -8,6 +8,7 @@ from litex.soc.interconnect import stream
 from usb3_pipe.lfps import LFPSUnit
 from usb3_pipe.training import TSUnit
 from usb3_pipe.ltssm import LTSSM
+from usb3_pipe.scrambling import Scrambler, Descrambler
 
 # USB3 PIPE ----------------------------------------------------------------------------------------
 
@@ -40,3 +41,22 @@ class USB3PIPE(Module):
         self.comb += ltssm.reset.eq(~self.enable)
         self.submodules.ltssm = ltssm
         self.comb += self.ready.eq(ltssm.polling_fsm.idle)
+
+        # Scrambling -------------------------------------------------------------------------------
+        scrambler = Scrambler()
+        scrambler = ResetInserter()(scrambler)
+        self.comb += scrambler.reset.eq(~self.enable)
+        self.submodules.scrambler = scrambler
+        self.comb += [
+            self.sink.connect(scrambler.sink),
+            If(self.ready, scrambler.source.connect(serdes.sink))
+        ]
+
+        descrambler = Descrambler()
+        descrambler = ResetInserter()(descrambler)
+        self.comb += descrambler.reset.eq(~self.enable)
+        self.submodules.descrambler = descrambler
+        self.comb += [
+            If(self.ready, serdes.source.connect(descrambler.sink)),
+            descrambler.source.connect(self.source),
+        ]
diff --git a/usb3_pipe/scrambling.py b/usb3_pipe/scrambling.py
index 670a091..e6e29a3 100644
--- a/usb3_pipe/scrambling.py
+++ b/usb3_pipe/scrambling.py
@@ -80,7 +80,6 @@ class ScramblerUnit(Module):
 
 # Scrambler ----------------------------------------------------------------------------------------
 
-@ResetInserter()
 class Scrambler(Module):
     def __init__(self):
         self.sink   =   sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
@@ -98,7 +97,6 @@ class Scrambler(Module):
 
 # Descrambler --------------------------------------------------------------------------------------
 
-@ResetInserter()
 class Descrambler(Module):
     def __init__(self):
         self.sink   =   sink = stream.Endpoint([("data", 32), ("ctrl", 4)])