diff --git a/sim.py b/sim.py
index 6289e42..d33f30b 100755
--- a/sim.py
+++ b/sim.py
@@ -48,7 +48,10 @@ class USB3PIPESim(SoCMini):
 
         # USB3 Host
         host_usb3_serdes = USB3SerDesModel()
-        host_usb3_pipe   = USB3PIPE(serdes=host_usb3_serdes, sys_clk_freq=sys_clk_freq)
+        host_usb3_pipe   = USB3PIPE(
+            serdes          = host_usb3_serdes,
+            sys_clk_freq    = sys_clk_freq,
+            with_scrambling = True)
         self.submodules += host_usb3_serdes, host_usb3_pipe
         self.comb += host_usb3_pipe.sink.valid.eq(1)
         self.comb += host_usb3_pipe.source.ready.eq(1)
@@ -56,7 +59,10 @@ class USB3PIPESim(SoCMini):
 
         # USB3 Device
         dev_usb3_serdes = USB3SerDesModel()
-        dev_usb3_pipe   = USB3PIPE(serdes=dev_usb3_serdes, sys_clk_freq=sys_clk_freq)
+        dev_usb3_pipe   = USB3PIPE(
+            serdes          = dev_usb3_serdes,
+            sys_clk_freq    = sys_clk_freq,
+            with_scrambling = True)
         self.submodules += dev_usb3_serdes, dev_usb3_pipe
         self.comb += dev_usb3_pipe.sink.valid.eq(1)
         self.comb += dev_usb3_pipe.source.ready.eq(1)
diff --git a/usb3_pipe/scrambling.py b/usb3_pipe/scrambling.py
index 6d2142c..e74948a 100644
--- a/usb3_pipe/scrambling.py
+++ b/usb3_pipe/scrambling.py
@@ -114,13 +114,11 @@ class Descrambler(Module):
 
         sync   = Signal()
         synced = Signal()
-        self.comb += sync.eq(sink.valid & (sink.data == scrambler.source.data))
+        self.comb += sync.eq(sink.data == scrambler.source.data)
         self.sync += If(sync, synced.eq(1))
         self.comb += [
-            If(~sync & ~synced,
-                sink.ready.eq(1)
-            ).Else(
-                sink.connect(scrambler.sink)
-            ),
+            sink.ready.eq(1),
+            sink.connect(scrambler.sink),
+            scrambler.sink.valid.eq(sink.valid & (sync | synced)),
             scrambler.source.connect(source)
         ]