mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
targets: update/simplify (programmers are now directly provided in litex-boards).
This commit is contained in:
Florent Kermarrec
parent
d66a782a95
commit
dd4d21f280
16
kc705.py
16
kc705.py
@ -183,13 +183,6 @@ class USB3SoC(SoCMini):
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
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self.add_csr("analyzer")
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# Load ---------------------------------------------------------------------------------------------
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def load():
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prog = VivadoProgrammer()
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prog.load_bitstream("build/gateware/top.bit")
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exit()
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# Build --------------------------------------------------------------------------------------------
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import argparse
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@ -207,18 +200,19 @@ def main():
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if args.build:
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print("[build]...")
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os.makedirs("build/gateware", exist_ok=True)
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os.makedirs("build/kc705/gateware", exist_ok=True)
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os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
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os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
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os.system("cp usb3_core/daisho/usb3/*.init build/kc705/gateware/")
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platform = kc705.Platform()
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platform.add_extension(_usb3_io)
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soc = USB3SoC(platform)
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builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
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builder = Builder(soc, csr_csv="tools/csr.csv")
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builder.build()
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if args.load:
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print("[load]...")
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load()
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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38
netv2.py
38
netv2.py
@ -133,34 +133,6 @@ class USB3SoC(SoCMini):
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
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self.add_csr("analyzer")
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# Load ---------------------------------------------------------------------------------------------
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def load():
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import os
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f = open("netv2.cfg", "w")
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f.write(
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"""
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interface bcm2835gpio
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transport select jtag
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bcm2835gpio_peripheral_base 0x3F000000
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bcm2835gpio_speed_coeffs 100000 5
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bcm2835gpio_jtag_nums 4 17 27 22
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bcm2835gpio_srst_num 24
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reset_config none
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source [find cpld/xilinx-xc7.cfg]
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adapter_khz 10000
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proc fpga_program {} {
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global _CHIPNAME
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xc7_program $_CHIPNAME.tap
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}
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""")
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f.close()
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from litex.build.openocd import OpenOCD
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prog = OpenOCD("netv2.cfg")
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prog.load_bitstream("build/gateware/top.bit")
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# Build --------------------------------------------------------------------------------------------
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import argparse
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@ -179,18 +151,18 @@ def main():
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if args.build:
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print("[build {}]...".format(args.device))
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os.makedirs("build/gateware", exist_ok=True)
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os.makedirs("build/netv2/gateware", exist_ok=True)
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os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
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os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
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os.system("cp usb3_core/daisho/usb3/*.init build/netv2/gateware/")
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platform = netv2.Platform(device=args.device)
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platform.add_extension(_usb3_io)
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soc = USB3SoC(platform)
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builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
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builder = Builder(soc, csr_csv="tools/csr.csv")
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builder.build()
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if args.load:
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print("[load]...")
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load()
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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@ -134,13 +134,6 @@ class USB3SoC(SoCMini):
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
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self.add_csr("analyzer")
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# Load ---------------------------------------------------------------------------------------------
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def load():
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prog = VivadoProgrammer()
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prog.load_bitstream("build/gateware/top.bit")
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exit()
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# Build --------------------------------------------------------------------------------------------
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import argparse
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@ -158,18 +151,19 @@ def main():
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if args.build:
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print("[build]...")
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os.makedirs("build/gateware", exist_ok=True)
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os.makedirs("build/pcie_screamer/gateware", exist_ok=True)
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os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
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os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
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os.system("cp usb3_core/daisho/usb3/*.init build/pcie_screamer/gateware/")
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platform = pcie_screamer.Platform()
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platform.add_extension(_usb3_io)
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soc = USB3SoC(platform)
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builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
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builder = Builder(soc, csr_csv="tools/csr.csv")
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builder.build()
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if args.load:
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print("[load]...")
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load()
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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4
sim.py
4
sim.py
@ -200,10 +200,10 @@ def main():
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sim_config = SimConfig(default_clk="sys_clk")
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os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
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os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
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os.system("cp usb3_core/daisho/usb3/*.init build/sim/gateware/")
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soc = USB3PIPESim()
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builder = Builder(soc, output_dir="build")
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builder = Builder(soc)
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builder.build(sim_config=sim_config,
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opt_level = "O0",
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trace = args.trace,
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@ -186,25 +186,6 @@ class USB3SoC(SoCMini):
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
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self.add_csr("analyzer")
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# Load ---------------------------------------------------------------------------------------------
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def load():
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import os
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f = open("ecp5-versa5g.cfg", "w")
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f.write(
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"""
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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adapter_khz 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
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""")
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f.close()
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os.system("openocd -f ecp5-versa5g.cfg -c \"transport select jtag; init; svf build/gateware/top.svf; exit\"")
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exit()
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# Build --------------------------------------------------------------------------------------------
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import argparse
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@ -233,7 +214,8 @@ def main():
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if args.load:
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print("[load]...")
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load()
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
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if __name__ == "__main__":
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main()
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