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pocs/kc705: add TSEQ Receiver, TS1 Receiver

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This commit is contained in:
Florent Kermarrec 2019-10-03 18:25:35 +02:00
parent 43f089281d
commit e4ffdaf9fc
2 changed files with 35 additions and 7 deletions
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25
pocs/kc705/kc705.py
View File

@ -19,8 +19,10 @@ from litex.boards.platforms import kc705
from litescope import LiteScopeAnalyzer
from usb3_pipe.common import TSEQ, TS1
from usb3_pipe.gtx_7series import GTXChannelPLL, GTX
from usb3_pipe.lfps import LFPSReceiver, LFPSTransmitter
from usb3_pipe.ordered_set import OrderedSetReceiver
# USB3 IOs -----------------------------------------------------------------------------------------
@ -165,6 +167,18 @@ class USB3SoC(SoCMini):
gtx.tx_pattern.eq(lfps_transmitter.tx_pattern),
]
# TSEQ Receiver ----------------------------------------------------------------------------
tseq_receiver = OrderedSetReceiver(ordered_set=TSEQ, n_ordered_sets=1024, data_width=32)
tseq_receiver = ClockDomainsRenamer("rx")(tseq_receiver)
self.submodules += tseq_receiver
self.comb += gtx.source.connect(tseq_receiver.sink)
# TS1 Receiver ----------------------------------------------------------------------------
ts1_receiver = OrderedSetReceiver(ordered_set=TS1, n_ordered_sets=1, data_width=32)
ts1_receiver = ClockDomainsRenamer("rx")(ts1_receiver)
self.submodules += ts1_receiver
self.comb += gtx.source.connect(ts1_receiver.sink)
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(gtx.tx_ready)
self.comb += platform.request("user_led", 1).eq(gtx.rx_ready)
@ -176,7 +190,7 @@ class USB3SoC(SoCMini):
platform.request("user_led", 2).eq(~polling_timer.done)
]
# LFPS Analyzer ---------------------------------------------------------------------------------
# LFPS Analyzer ----------------------------------------------------------------------------
if with_lfps_analyzer:
analyzer_signals = [
rxelecidle,
@ -192,7 +206,14 @@ class USB3SoC(SoCMini):
# RX Analyzer ---------------------------------------------------------------------------------
if with_rx_analyzer:
analyzer_signals = [gtx.source]
analyzer_signals = [
gtx.source,
tseq_receiver.detected,
ts1_receiver.detected,
ts1_receiver.reset,
ts1_receiver.loopback,
ts1_receiver.scrambling,
]
self.submodules.rx_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="rx", csr_csv="rx_analyzer.csv")
self.add_csr("rx_analyzer")

17
pocs/kc705/test_rx_analyzer.py
View File

@ -6,7 +6,7 @@ import time
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
from usb3_pipe.common import TSEQ
from usb3_pipe.common import TSEQ, TS1
wb = RemoteClient()
wb.open()
@ -14,6 +14,8 @@ wb.open()
# # #
TSEQ_FIRST_WORD = int.from_bytes(TSEQ.to_bytes()[0:4], byteorder="little")
TS1_FIRST_WORD = int.from_bytes(TS1.to_bytes()[0:4], byteorder="little")
print("%08x" %TS1_FIRST_WORD)
# FPGA ID ------------------------------------------------------------------------------------------
fpga_id = ""
@ -28,17 +30,22 @@ print("FPGA: " + fpga_id)
wb.regs.gtx_rx_polarity.write(1)
wb.regs.gtx_tx_enable.write(1)
while (wb.regs.gtx_tx_ready.read() == 0):
pass
pass
wb.regs.gtx_rx_enable.write(1)
while (wb.regs.gtx_rx_ready.read() == 0):
pass
pass
# Analyzer dump ------------------------------------------------------------------------------------
analyzer = LiteScopeAnalyzerDriver(wb.regs, "rx_analyzer", debug=True)
analyzer.configure_subsampler(1)
analyzer.configure_trigger(cond={
"soc_source_payload_ctrl": 1,
"soc_source_payload_data": TSEQ_FIRST_WORD})
"soc_gtx0_source_payload_ctrl": 0b0001,
"soc_gtx0_source_payload_data": TSEQ_FIRST_WORD})
analyzer.configure_trigger(cond={
"soc_gtx0_source_payload_ctrl": 0b1111,
"soc_gtx0_source_payload_data": TS1_FIRST_WORD})
#analyzer.configure_trigger(cond={"soc_tseq_receiver_detected": 1})
#analyzer.configure_trigger(cond={"soc_ts1_receiver_detected": 1})
analyzer.run(offset=32, length=4096)
analyzer.wait_done()
analyzer.upload()