FPGA/usb3_pipe
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sim: set opt_level to O0 (reduce compilation time)

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Florent Kermarrec 2019-10-31 19:29:54 +01:00
parent 96c02aa56e
commit e9b87dae42
1 changed files with 1 additions and 1 deletions
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2
sim.py
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@ -105,7 +105,7 @@ def main():
soc = USB3PIPESim()
builder = Builder(soc, output_dir="build")
builder.build(sim_config=sim_config, trace=args.trace)
builder.build(sim_config=sim_config, trace=args.trace, opt_level="O0")
if __name__ == "__main__":