FPGA/usb3_pipe
1
0
Fork 0
mirror of https://github.com/enjoy-digital/usb3_pipe.git synced 2025-01-04 10:18:41 +08:00
Code Issues Projects Releases Wiki Activity

serdes: simplify SerdesRXAligner

Browse Source
This commit is contained in:
Florent Kermarrec 2019-10-08 10:02:33 +02:00
parent 537074d942
commit ec3b7e9c57
1 changed files with 14 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
usb3_pipe/serdes.py
View File

@ -78,41 +78,24 @@ class SerdesRXAligner(stream.PipelinedActor):
]
# Alignment detection
self.sync += [
If(self.enable & sink.valid & self.pipe_ce,
If(sink.ctrl[0] & (sink.data[0:8] == COM.value),
alignment.eq(0)
),
If(sink.ctrl[1] & (sink.data[8:16] == COM.value),
alignment.eq(1)
),
If(sink.ctrl[2] & (sink.data[16:24] == COM.value),
alignment.eq(2)
),
If(sink.ctrl[3] & (sink.data[24:32] == COM.value),
alignment.eq(3)
for i in range(4):
self.sync += [
If(self.enable & sink.valid & self.pipe_ce,
If(sink.ctrl[i] & (sink.data[8*i:8*(i+1)] == COM.value),
alignment.eq(i)
)
)
)
]
]
# Do the alignment
data = Cat(last_data, sink.data)
ctrl = Cat(last_ctrl, sink.ctrl)
cases = {}
cases[0] = [
source.data.eq(last_data),
source.ctrl.eq(last_ctrl)
]
cases[1] = [
source.data.eq(Cat(last_data[8:32], sink.data[0:8])),
source.ctrl.eq(Cat(last_ctrl[1:4], sink.ctrl[0:1])),
]
cases[2] = [
source.data.eq(Cat(last_data[16:32], sink.data[0:16])),
source.ctrl.eq(Cat(last_ctrl[2:4], sink.ctrl[0:2])),
]
cases[3] = [
source.data.eq(Cat(last_data[24:32], sink.data[0:24])),
source.ctrl.eq(Cat(last_ctrl[3:4], sink.ctrl[0:3])),
]
for i in range(4):
cases[i] = [
source.data.eq(data[8*i:]),
source.ctrl.eq(ctrl[i:]),
]
self.comb += Case(alignment, cases)
# Kintex7 USB3 Serializer/Deserializer -------------------------------------------------------------