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serdes: rename RXSkipPRemover/TXSkipInserter to RXSKPRemover/TXSKPInserter

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This commit is contained in:
Florent Kermarrec 2019-12-05 12:07:06 +01:00
parent 22fc42a9b9
commit ed13585466
1 changed files with 6 additions and 6 deletions
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12
usb3_pipe/serdes.py
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@ -8,9 +8,9 @@ from litex.soc.cores.code_8b10b import Encoder, Decoder
from usb3_pipe.common import K, COM, SKP
# RX Skip Remover ----------------------------------------------------------------------------------
# RX SKP Remover -----------------------------------------------------------------------------------
class RXSkipRemover(Module):
class RXSKPRemover(Module):
def __init__(self):
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
@ -151,9 +151,9 @@ class RXSubstitution(Module):
)
]
# TX Skip Inserter ---------------------------------------------------------------------------------
# TX SKP Inserter ----------------------------------------------------------------------------------
class TXSkipInserter(Module):
class TXSKPInserter(Module):
def __init__(self):
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
@ -220,7 +220,7 @@ class SerdesTXDatapath(Module):
# # #
skip_inserter = TXSkipInserter()
skip_inserter = TXSKPInserter()
self.submodules += skip_inserter
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8)
cdc = ClockDomainsRenamer({"write": "sys", "read": clock_domain})(cdc)
@ -256,7 +256,7 @@ class SerdesRXDatapath(Module):
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8)
cdc = ClockDomainsRenamer({"write": clock_domain, "read": "sys"})(cdc)
self.submodules.cdc = cdc
skip_remover = RXSkipRemover()
skip_remover = RXSKPRemover()
self.submodules.skip_remover = skip_remover
word_aligner = RXWordAligner()
self.submodules.word_aligner = word_aligner