FPGA/usb3_pipe
1
0
Fork 0
mirror of https://github.com/enjoy-digital/usb3_pipe.git synced 2025-01-04 10:18:41 +08:00
Code Issues Projects Releases Wiki Activity

serdes: rename RXSkipPRemover/TXSkipInserter to RXSKPRemover/TXSKPInserter

Browse Source
This commit is contained in:
Florent Kermarrec 2019-12-05 12:07:06 +01:00
parent 22fc42a9b9
commit ed13585466
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
usb3_pipe/serdes.py
View File

@ -8,9 +8,9 @@ from litex.soc.cores.code_8b10b import Encoder, Decoder
from usb3_pipe.common import K, COM, SKP from usb3_pipe.common import K, COM, SKP
# RX Skip Remover ---------------------------------------------------------------------------------- # RX SKP Remover -----------------------------------------------------------------------------------
class RXSkipRemover(Module): class RXSKPRemover(Module):
def __init__(self): def __init__(self):
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)]) self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)]) self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
@ -151,9 +151,9 @@ class RXSubstitution(Module):
) )
] ]
# TX Skip Inserter --------------------------------------------------------------------------------- # TX SKP Inserter ----------------------------------------------------------------------------------
class TXSkipInserter(Module): class TXSKPInserter(Module):
def __init__(self): def __init__(self):
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)]) self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)]) self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
@ -220,7 +220,7 @@ class SerdesTXDatapath(Module):
# # # # # #
skip_inserter = TXSkipInserter() skip_inserter = TXSKPInserter()
self.submodules += skip_inserter self.submodules += skip_inserter
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8) cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8)
cdc = ClockDomainsRenamer({"write": "sys", "read": clock_domain})(cdc) cdc = ClockDomainsRenamer({"write": "sys", "read": clock_domain})(cdc)
@ -256,7 +256,7 @@ class SerdesRXDatapath(Module):
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8) cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 8)
cdc = ClockDomainsRenamer({"write": clock_domain, "read": "sys"})(cdc) cdc = ClockDomainsRenamer({"write": clock_domain, "read": "sys"})(cdc)
self.submodules.cdc = cdc self.submodules.cdc = cdc
skip_remover = RXSkipRemover() skip_remover = RXSKPRemover()
self.submodules.skip_remover = skip_remover self.submodules.skip_remover = skip_remover
word_aligner = RXWordAligner() word_aligner = RXWordAligner()
self.submodules.word_aligner = word_aligner self.submodules.word_aligner = word_aligner