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pcie_screamer: fix build, use user_btn0 as reset

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This commit is contained in:
Florent Kermarrec 2019-11-08 14:35:17 +01:00
parent 52b7980f28
commit ef770d5f71
1 changed files with 7 additions and 2 deletions
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9
pcie_screamer.py
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@ -30,6 +30,9 @@ _io = [
("user_btn", 0, Pins("AA1"), IOStandard("LVCMOS33")), ("user_btn", 0, Pins("AA1"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("AB6"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("AB6"), IOStandard("LVCMOS33")),
("user_gpio", 0, Pins("Y6"), IOStandard("LVCMOS33")),
("user_gpio", 1, Pins("AA6"), IOStandard("LVCMOS33")),
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("T1")), Subsignal("tx", Pins("T1")),
Subsignal("rx", Pins("U1")), Subsignal("rx", Pins("U1")),
@ -58,7 +61,7 @@ class Platform(XilinxPlatform):
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_oob = ClockDomain() self.clock_domains.cd_usb3_oob = ClockDomain()
self.clock_domains.cd_clk125 = ClockDomain() self.clock_domains.cd_clk125 = ClockDomain()
# # # # # #
@ -70,9 +73,10 @@ class _CRG(Module):
self.cd_clk125.clk.attr.add("keep") self.cd_clk125.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-2) self.submodules.pll = pll = S7PLL(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("user_btn", 0))
pll.register_clkin(clk100, 100e6) pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_oob, sys_clk_freq/8) pll.create_clkout(self.cd_usb3_oob, sys_clk_freq/8)
pll.create_clkout(self.cd_clk125, 125e6) pll.create_clkout(self.cd_clk125, 125e6)
# USB3SoC ------------------------------------------------------------------------------------------ # USB3SoC ------------------------------------------------------------------------------------------
@ -99,6 +103,7 @@ class USB3SoC(SoCMini):
tx_pads = platform.request("pcie_tx"), tx_pads = platform.request("pcie_tx"),
rx_pads = platform.request("pcie_rx")) rx_pads = platform.request("pcie_rx"))
self.submodules += usb3_serdes self.submodules += usb3_serdes
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# USB3 PHY --------------------------------------------------------------------------------- # USB3 PHY ---------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq) usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)