17 Commits

Author	SHA1	Message	Date
Florent Kermarrec	445d8d183c	serdes: document, rename SerdesTXDatapath/SerdesRXDatapath to TXDatapath/RXDatapath	2019-12-13 14:56:25 +01:00
Florent Kermarrec	22fc42a9b9	training: add ts1_inv_checker and use it to detect rx polarity	2019-12-04 21:01:27 +01:00
Florent Kermarrec	fe494fccda	sim: make phy_dw configurable	2019-11-29 14:45:00 +01:00
Florent Kermarrec	8cb9cfd6ee	sim: add trace-start/trace-end	2019-11-29 13:56:35 +01:00
Florent Kermarrec	56811680a2	usb3_core: make sure we generate the USB3 descriptors before the build or simulation	2019-11-29 13:00:15 +01:00
Florent Kermarrec	8732c59a57	sim: integrate USB3Core	2019-11-22 14:32:12 +01:00
Florent Kermarrec	40d158f6b7	serdes: move USB3SerDesModel to sim.py	2019-11-12 13:21:46 +01:00
Florent Kermarrec	e9b87dae42	sim: set opt_level to O0 (reduce compilation time)	2019-10-31 19:30:07 +01:00
Florent Kermarrec	dbb756baaa	scrambling: simplify Descrambler, fixes sim	2019-10-29 21:56:48 +01:00
Florent Kermarrec	6237110476	ltssm: remove _fsm suffix for FSMs	2019-10-16 15:51:35 +02:00
Florent Kermarrec	c39ed5f38c	core/USB3PIPE: integrate scrambler/descrambler	2019-10-10 10:35:01 +02:00
Florent Kermarrec	1dc029fabc	sim: delay end of simulation to ease visualize the end on the trace	2019-10-10 09:42:09 +02:00
Florent Kermarrec	0957fc3958	sim: add display of polling fsm transitions	2019-10-10 09:33:03 +02:00
Florent Kermarrec	1bd83c3ea4	sim/lfps: now working in simulation	2019-10-09 19:03:18 +02:00
Florent Kermarrec	8803c75bbd	sim/ltssm: rework/simplify polling fsm, going to polling idle in simulation	2019-10-09 18:40:05 +02:00
Florent Kermarrec	05e30be3ee	sim: add Host/Device USB3 PIPE	2019-10-09 12:55:16 +02:00
Florent Kermarrec	f43b3a4c8b	add litex/verilator sim skeleton	2019-10-09 12:49:00 +02:00