Florent Kermarrec
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dbb756baaa
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scrambling: simplify Descrambler, fixes sim
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2019-10-29 21:56:48 +01:00 |
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Florent Kermarrec
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daf447e0fc
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serdes/USB3SerDesModel: add tx/rx_polarity support
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2019-10-29 21:35:18 +01:00 |
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Florent Kermarrec
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63e485e5e6
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serdes/USB3SerDesModel: add 8b10b encoders/decoders
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2019-10-29 21:27:23 +01:00 |
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Florent Kermarrec
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c0a95e1c0d
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targets: remove rx_tseq from analyzer, pass ip_address to liteeth as str (liteeth can now convert it directly to int)
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2019-10-29 21:04:25 +01:00 |
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Florent Kermarrec
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1405ee3525
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core: remove enable signal to simplify, CEInserter or ResetInserter could be used on USB3PIPE is needed
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2019-10-29 20:55:17 +01:00 |
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Florent Kermarrec
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4c119d730c
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training: simplify TSChecker (we only need to support ts1/ts2)
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2019-10-29 20:49:31 +01:00 |
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Florent Kermarrec
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d4507ebf02
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training: remove tseq checker (we only need to check ts1/ts2)
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2019-10-29 20:47:00 +01:00 |
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Florent Kermarrec
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01c43225f0
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serdes: increase cdc depth (needed for ECP5)
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2019-10-18 19:52:21 +02:00 |
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Florent Kermarrec
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bc8d458a9a
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serdes: use stream.BufferizeEndpoints to improve timings
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2019-10-18 19:09:30 +02:00 |
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Florent Kermarrec
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a3fe22b5a7
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versa_ecp5: revert ethernet (faster to get debug traces)
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2019-10-18 15:22:25 +02:00 |
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Florent Kermarrec
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0cb086d924
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versa_ecp5: fix ispclk control, use channel 0 (pcie), add clocks debug leds
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2019-10-18 14:56:10 +02:00 |
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Florent Kermarrec
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a5f94f1f0c
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serdes/ECP5USB3SerDes: add channel parameter
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2019-10-18 14:47:55 +02:00 |
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Florent Kermarrec
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ed64134e2c
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add load script for ecp5_versa, rename load to load_xilinx
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2019-10-18 14:32:04 +02:00 |
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Florent Kermarrec
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95a42f8d92
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versa_ecp5: debug over serial instead of ethernet, disable scrambling and use trellis toolchain
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2019-10-18 14:16:03 +02:00 |
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Florent Kermarrec
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bd24f207c5
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serdes: use tx/rx_clk_freq for timing constraints, remove electrical idle FIXME
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2019-10-18 14:14:36 +02:00 |
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Florent Kermarrec
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4a001e7479
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core: add with_scrambling parameter to allow disabling it
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2019-10-18 14:14:00 +02:00 |
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Florent Kermarrec
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712903d0f5
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serdes/ECP5USB3SerDes: increase linerate to 5gbps, connect tx_idle/rx_idle
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2019-10-17 19:28:46 +02:00 |
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Florent Kermarrec
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6237110476
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ltssm: remove _fsm suffix for FSMs
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2019-10-16 15:51:35 +02:00 |
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Florent Kermarrec
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5d23beab97
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ltssm: implement PollingFSM according to specification (untested)
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2019-10-16 11:39:45 +02:00 |
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Florent Kermarrec
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00db986239
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targets: fix #!/usr/bin/env python3 location
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2019-10-15 15:48:12 +02:00 |
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Florent Kermarrec
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cc26d47780
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add initial ecp5 support with versa_ecp5 board (not working, serdes at 2.5gbps, only for testing LFPS for now)
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2019-10-15 15:46:55 +02:00 |
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Florent Kermarrec
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a5e5735f12
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tools/test_analyzer: add more triggers
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2019-10-10 18:24:19 +02:00 |
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Florent Kermarrec
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86be7b76d6
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serdes: expose rx_skip to user (for observation)
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2019-10-10 18:23:46 +02:00 |
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Florent Kermarrec
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91b14f26a5
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training: fix default scrambling value
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2019-10-10 18:01:53 +02:00 |
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Florent Kermarrec
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087855bf46
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training: fix TS1/TS2 loopback/scrambling mapping
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2019-10-10 17:45:00 +02:00 |
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Florent Kermarrec
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ea3ef66fe7
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ltssm: remove initial count, hack for hardware tests
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2019-10-10 17:16:35 +02:00 |
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Florent Kermarrec
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d1f3a347df
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core: use Descrambler, disable Scrambler/Descrambler until ready is set
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2019-10-10 17:16:13 +02:00 |
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Florent Kermarrec
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7fd9120181
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scrambling: add Descrambler (Scrambler + Auto-Synchronization)
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2019-10-10 17:15:18 +02:00 |
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Florent Kermarrec
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32030ed5fc
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tools/test_analyzer: use rising_edge triggers
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2019-10-10 17:14:37 +02:00 |
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Florent Kermarrec
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4298c6611b
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kc705: add more signals to analyzer
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2019-10-10 17:14:14 +02:00 |
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Florent Kermarrec
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5b766266c9
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training/TSGenerator: test/fix control backpressure
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2019-10-10 15:32:23 +02:00 |
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Florent Kermarrec
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801ee05a94
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ltssm/training: test with hardware, some fixes
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2019-10-10 13:54:09 +02:00 |
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Florent Kermarrec
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c961ac706e
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kc705: remove scrambler/ idle trigger, add more signals to analyzer
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2019-10-10 13:53:21 +02:00 |
|
Florent Kermarrec
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630ce0edd1
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scrambling: add enable
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2019-10-10 10:51:14 +02:00 |
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Florent Kermarrec
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01a942ca7b
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scrambling: don't scramble K codes, only keep Scrambler (Descrambler is simular)
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2019-10-10 10:50:02 +02:00 |
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Florent Kermarrec
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c39ed5f38c
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core/USB3PIPE: integrate scrambler/descrambler
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2019-10-10 10:35:01 +02:00 |
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Florent Kermarrec
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d27639c927
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training/TSGenerator: pulse done signal on last generator cycle
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2019-10-10 10:34:27 +02:00 |
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Florent Kermarrec
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1dc029fabc
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sim: delay end of simulation to ease visualize the end on the trace
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2019-10-10 09:42:09 +02:00 |
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Florent Kermarrec
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0957fc3958
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sim: add display of polling fsm transitions
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2019-10-10 09:33:03 +02:00 |
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Florent Kermarrec
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2b2f74c4dd
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test/test_training: fix
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2019-10-09 19:18:35 +02:00 |
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Florent Kermarrec
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104b62390d
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README.md: center logo, add Migen/LiteX
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2019-10-09 19:17:06 +02:00 |
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Florent Kermarrec
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1bd83c3ea4
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sim/lfps: now working in simulation
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2019-10-09 19:03:18 +02:00 |
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Florent Kermarrec
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8803c75bbd
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sim/ltssm: rework/simplify polling fsm, going to polling idle in simulation
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2019-10-09 18:40:05 +02:00 |
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Florent Kermarrec
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05e30be3ee
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sim: add Host/Device USB3 PIPE
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2019-10-09 12:55:16 +02:00 |
|
Florent Kermarrec
|
c77296f798
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serdes: add USB3SerDesModel
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2019-10-09 12:54:36 +02:00 |
|
Florent Kermarrec
|
f43b3a4c8b
|
add litex/verilator sim skeleton
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2019-10-09 12:49:00 +02:00 |
|
Florent Kermarrec
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9c4af5ff69
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training: add tseq/ts1 generator (to be able to simulate the host, will be simplified at synthesis is not used)
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2019-10-09 12:32:30 +02:00 |
|
Florent Kermarrec
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8b5e07e3c9
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add __init__.py to simplify imports
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2019-10-09 12:17:30 +02:00 |
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Florent Kermarrec
|
8bef6fcbc6
|
rename phy to core and USB3PHY to USB3PIPE
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2019-10-09 12:12:48 +02:00 |
|
Florent Kermarrec
|
f763c282ea
|
serdes: fix typo
|
2019-10-09 12:12:16 +02:00 |
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