mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
121 lines
5.2 KiB
Markdown
121 lines
5.2 KiB
Markdown
```
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__ _________ ____ ___ _______ ____
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/ / / / __/ _ )|_ /___/ _ \/ _/ _ \/ __/
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/ /_/ /\ \/ _ |/_ <___/ ___// // ___/ _/
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\____/___/____/____/ /_/ /___/_/ /___/
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Copyright (c) 2019-2022, EnjoyDigital
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Powered by LiteX
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```
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[](https://travis-ci.com/enjoy-digital/usb3_pipe)
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[> Intro
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--------
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The aim of this project is to experiment with [High Speed Transceivers (SERDES)](https://en.wikipedia.org/wiki/Multi-gigabit_transceiver) of popular FPGAs to create a [USB3.0 PIPE interface](https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/phy-interface-pci-express-sata-usb30-architectures-3.1.pdf).
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Current solutions for USB3 connectivity with an FPGA require the use of an external SerDes chip ([TI TUSB1310A - SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces](http://www.ti.com/product/TUSB1310A)) or external FIFO chip ([FTDI FT60X](https://www.ftdichip.com/Products/ICs/FT600.html) or Cypress [FX3](https://www.cypress.com/products/ez-usb-fx3-superspeed-usb-30-peripheral-controller)). With this project, we want to see if it's possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip!)
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[> Targets
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----------
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While we hope this wrapper will eventually support multiple protocols through the PIPE interface (such as PCIe, SATA, DisplayPort) it is currently targeting support for [USB3.0 SuperSpeed](https://en.wikipedia.org/wiki/USB_3.0#Data_encoding) when used with a customized [Daisho USB3 core](https://github.com/enjoy-digital/daisho).
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It currently targets Xilinx Kintex7 and Artix7.
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[> Test Hardware
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----------------
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One of the following boards:
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- [KC705](https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html)
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- [LiteX Acorn Baseboard](https://github.com/enjoy-digital/litex-acorn-baseboard)
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paired with the [SFP2USB](http://xillybus.com/sfp2usb-module) borrowed from [XillyUSB](http://xillybus.com/xillyusb) project:
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or with the [SFP2USBPCIsh-to-USB3.0](https://github.com/enjoy-digital/usb3_pipe/blob/master/doc/breakout_board.pdf) breakout board:
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**Note:** Any 7-Series board with a SFP or PCIe connector with also be suitable but will require creating a platform/target file if not already supported in [LiteX-Boards](https://github.com/litex-hub/litex-boards).
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[> Toolchain
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------------
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This project targets Xilinx Vivado for Kintex7 / Artix7 support. In the future, it should also be possible to use [F4PGA](https://f4pga.org/) toolchains to build the design.
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[> Prerequisites
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----------------
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```sh
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$ sudo apt install build-essential wget git python3-setuptools
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$ git clone https://github.com/enjoy-digital/usb3_pipe/
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$ cd usb3_pipe
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```
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[> Installing LiteX
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-------------------
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Follow LiteX installation [guide](https://github.com/enjoy-digital/litex/wiki/Installation).
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[> Installing Verilator
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-----------------------
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```sh
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$ sudo apt install verilator
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$ sudo apt install libevent-dev libjson-c-dev
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```
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[> Running the LiteX simulation
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-------------------------------
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```sh
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$ ./sim.py
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```
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You should see the USB3.0 initialization between a Host and Device:
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```
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[00000000] HOST entering Polling.LFPS state
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[00000000] DEV entering Polling.LFPS state
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[00000000] HOST entering Polling.LFPS state
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[00000000] DEV entering Polling.LFPS state
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[00026641] HOST entering Polling.RxEQ state
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[00026641] DEV entering Polling.RxEQ state
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[01075207] HOST entering Polling.Active state
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[01075207] DEV entering Polling.Active state
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[01075296] HOST entering Polling.Configuration state
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[01075296] DEV entering Polling.Configuration state
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[01075423] HOST entering Polling.Idle state
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[01075423] DEV entering Polling.Idle state
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```
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At this point, all the steps of the USB3.0 PIPE initialization have succeeded and the USB3.0 Core can start transmitting packets.
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To have a .vcd waveform of the simulation, run it with --trace:
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```sh
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$ ./sim.py --trace
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$ gtkwave build/gateware/dut.vcd
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```
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[> Running on hardware
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----------------------
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### Build the FPGA bitstream
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Once installed, build the bitstream with:
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```sh
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$ ./target.py --build (can be kc705 or acorn)
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```
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### Prepare the hardware:
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- Put the SFP2USB module into the SFP cage of the board.
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- Connect the USB3.0 cable between the SFP2USB module and the computer.
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- Connect the JTAG programming cable to the FPGA board.
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- Power on the hardware
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### Load the FPGA bitstream
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To load the bitstream to you board, run:
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```sh
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$ ./target.py --load
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```
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### Verify USB3.0 link establishment
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Once the FPGA is loaded, the link will be automatically established with the computer and an Openmoko, Inc USB3.0 device should be enumerated.
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**Note:** Enumeration has only been done on a few hardware setups and there is still work in progress to improve reliability.
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