mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
137 lines
5.4 KiB
Python
137 lines
5.4 KiB
Python
# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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# USB3 Core Control --------------------------------------------------------------------------------
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class USB3CoreControl(Module, AutoCSR):
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def __init__(self):
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# Not functional but prevents synthesis optimizations
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self._buf_in_addr = CSRStorage(9)
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self._buf_in_data = CSRStorage(32)
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self._buf_in_wren = CSR()
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self._buf_in_request = CSRStatus()
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self._buf_in_ready = CSRStatus()
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self._buf_in_commit = CSR()
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self._buf_in_commit_len = CSRStorage(11)
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self._buf_in_commit_ack = CSRStatus()
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self._buf_out_addr = CSRStorage(9)
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self._buf_out_q = CSRStatus(32)
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self._buf_out_len = CSRStatus(11)
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self._buf_out_hasdata = CSRStatus()
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self._buf_out_arm = CSR()
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self._buf_out_arm_ack = CSRStatus()
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# # #
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self.buf_in_addr = self._buf_in_addr.storage
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self.buf_in_data = self._buf_in_data.storage
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self.buf_in_wren = self._buf_in_wren.re & self._buf_in_wren.r
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self.buf_in_request = self._buf_in_request.status
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self.buf_in_ready = self._buf_in_ready.status
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self.buf_in_commit = self._buf_in_commit.re & self._buf_in_commit.r
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self.buf_in_commit_len = self._buf_in_commit_len.storage
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self.buf_in_commit_ack = self._buf_in_commit_ack.status
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self.buf_out_addr = self._buf_out_addr.storage
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self.buf_out_q = self._buf_out_q.status
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self.buf_out_len = self._buf_out_len.status
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self.buf_out_hasdata = self._buf_out_hasdata.status
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self.buf_out_arm = self._buf_out_arm.re & self._buf_out_arm.r
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self.buf_out_arm_ack = self._buf_out_arm_ack.status
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# USB3 Core ----------------------------------------------------------------------------------------
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class USB3Core(Module, AutoCSR):
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def __init__(self, platform):
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self.reset = Signal()
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self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
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self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
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# # #
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self.submodules.usb3_control = usb3_control = USB3CoreControl()
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u0_timer = WaitTimer(32)
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u0_timer = ResetInserter()(u0_timer)
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self.submodules += u0_timer
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self.comb += u0_timer.wait.eq(1)
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self.comb += u0_timer.reset.eq(self.reset)
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LT_POLLING_IDLE = 15
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LT_POLLING_U0 = 16
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ltssm_state = Signal(5)
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self.comb += [
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If(~u0_timer.done,
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ltssm_state.eq(LT_POLLING_IDLE)
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).Else(
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ltssm_state.eq(LT_POLLING_U0)
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)
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]
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self.comb += sink.ready.eq(1)
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out_data = Signal(32)
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out_datak = Signal(4)
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out_stall = Signal()
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out_active = Signal()
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out_active_d = Signal()
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# FIXME: Source always supposed to be ready, which is not the case! Use this for now for
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# initial tests along with a sys_clk generated from the same source as the one used for
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# the TX transceiver
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self.comb += source.valid.eq(1)
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self.sync += [
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source.data.eq(out_data),
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source.ctrl.eq(out_datak),
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out_active_d.eq(out_active),
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source.first.eq(out_active & ~ out_active_d),
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]
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self.comb += source.last.eq(~out_active & out_active_d)
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self.specials += Instance("usb3_top_usb3_pipe",
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i_clk = ClockSignal(),
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i_reset_n = ~self.reset,
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i_ltssm_state = ltssm_state,
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i_in_data = sink.data,
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i_in_datak = sink.ctrl,
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i_in_active = sink.valid,
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o_out_data = out_data,
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o_out_datak = out_datak,
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o_out_active = out_active,
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i_out_stall = 0, # FIXME
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i_buf_in_addr = usb3_control.buf_in_addr,
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i_buf_in_data = usb3_control.buf_in_data,
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i_buf_in_wren = usb3_control.buf_in_wren,
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o_buf_in_request = usb3_control.buf_in_request,
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o_buf_in_ready = usb3_control.buf_in_ready,
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i_buf_in_commit = usb3_control.buf_in_commit,
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i_buf_in_commit_len = usb3_control.buf_in_commit_len,
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o_buf_in_commit_ack = usb3_control.buf_in_commit_ack,
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i_buf_out_addr = usb3_control.buf_out_addr,
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o_buf_out_q = usb3_control.buf_out_q,
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o_buf_out_len = usb3_control.buf_out_len,
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o_buf_out_hasdata = usb3_control.buf_out_hasdata,
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i_buf_out_arm = usb3_control.buf_out_arm,
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o_buf_out_arm_ack = usb3_control.buf_out_arm_ack,
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#o_vend_req_act =,
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#o_vend_req_request =,
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#o_vend_req_val =
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)
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daisho_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "daisho")
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platform.add_verilog_include_path(os.path.join(daisho_path))
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platform.add_verilog_include_path(os.path.join(daisho_path, "usb3"))
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platform.add_source_dir(os.path.join(daisho_path, "usb3"))
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