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           Copyright (c) 2019, EnjoyDigital

USB3 PIPE Experiments

The aim of this project is to experiment with High Speed Transceivers (SERDES) of popular FPGAs to create a USB3.0 PIPE interface.

Current solutions for USB3 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A - SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces) or external FIFO chip (FTDI FT60X or Cypress FX3). With this project, we want to see if it's possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip!)

Targets

While we hope this wrapper will eventually support multiple protocols through the PIPE interface (such as PCIe, SATA, DisplayPort) it is currently targeting support for USB3.0 SuperSpeed when used with a customized the Daisho USB3 core.

It currently targets Xilinx Kintex7, Artix7 and Lattice ECP5 FPGAs.

Test Hardware

One of the following boards:

• KC705
• PCIe Screamer
• Versa ECP5

paired with

• 3-Port USB 3 FMC Module from HiTechGlobal.
• [Modified PCIe riser] (link TBD)

Toolchain

This project targets;

• Xilinx Vivado for Kintex7 / Artix7 support
• Yosys + nextpnr for ECP5 support

There will also be a demo showing how to use a harness to expose the PIPE interface to the SymbiFlow Yosys + VPR flow.