mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
276 lines
13 KiB
Python
276 lines
13 KiB
Python
# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from litex.soc.interconnect.csr import *
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# USB3 Core ----------------------------------------------------------------------------------------
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class USB3Core(Module):
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def __init__(self, platform):
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# usb ios
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usb_reset_n = platform.request("usb_reset_n", usb_connector)
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if with_usb3:
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usb_pipe_ctrl = platform.request("usb_pipe_ctrl", usb_connector)
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usb_pipe_status = platform.request("usb_pipe_status", usb_connector)
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usb_pipe_data = platform.request("usb_pipe_data", usb_connector)
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usb3_reset_n = Signal(reset=1)
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self.comb += usb_reset_n.eq(usb3_reset_n)
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# usb3 core
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if with_usb3:
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class USB3Control(Module, AutoCSR):
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def __init__(self):
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self._phy_enable = CSRStorage()
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self._core_enable = CSRStorage()
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# probably not working but prevent synthesis optimizations
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self._buf_in_addr = CSRStorage(9)
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self._buf_in_data = CSRStorage(32)
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self._buf_in_wren = CSR()
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self._buf_in_request = CSRStatus()
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self._buf_in_ready = CSRStatus()
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self._buf_in_commit = CSR()
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self._buf_in_commit_len = CSRStorage(11)
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self._buf_in_commit_ack = CSRStatus()
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self._buf_out_addr = CSRStorage(9)
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self._buf_out_q = CSRStatus(32)
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self._buf_out_len = CSRStatus(11)
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self._buf_out_hasdata = CSRStatus()
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self._buf_out_arm = CSR()
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self._buf_out_arm_ack = CSRStatus()
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# # #
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self.phy_enable = self._phy_enable.storage
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self.core_enable = self._core_enable.storage
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self.buf_in_addr = self._buf_in_addr.storage
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self.buf_in_data = self._buf_in_data.storage
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self.buf_in_wren = self._buf_in_wren.re & self._buf_in_wren.r
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self.buf_in_request = self._buf_in_request.status
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self.buf_in_ready = self._buf_in_ready.status
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self.buf_in_commit = self._buf_in_commit.re & self._buf_in_commit.r
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self.buf_in_commit_len = self._buf_in_commit_len.storage
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self.buf_in_commit_ack = self._buf_in_commit_ack.status
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self.buf_out_addr = self._buf_out_addr.storage
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self.buf_out_q = self._buf_out_q.status
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self.buf_out_len = self._buf_out_len.status
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self.buf_out_hasdata = self._buf_out_hasdata.status
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self.buf_out_arm = self._buf_out_arm.re & self._buf_out_arm.r
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self.buf_out_arm_ack = self._buf_out_arm_ack.status
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self.submodules.usb3_control = USB3Control()
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self.add_csr("usb3_control")
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phy_pipe_pll_locked = Signal()
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phy_pipe_pll_fb = Signal()
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phy_pipe_half_clk_pll = Signal()
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phy_pipe_half_clk_phase_pll = Signal()
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phy_pipe_quarter_clk_pll = Signal()
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phy_pipe_tx_clk_phase_pll = Signal()
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phy_pipe_half_clk = Signal()
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phy_pipe_half_clk_phase = Signal()
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phy_pipe_quarter_clk = Signal()
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phy_pipe_tx_clk_phase = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=phy_pipe_pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=4.0,
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p_CLKFBOUT_MULT=4, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=usb_pipe_data.rx_clk, i_CLKFBIN=phy_pipe_pll_fb,
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o_CLKFBOUT=phy_pipe_pll_fb,
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# 125MHz: 1/2 PCLK
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=phy_pipe_half_clk_pll,
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# 125MHz: 1/2 PCLK, phase shift 90
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p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=90.0,
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o_CLKOUT1=phy_pipe_half_clk_phase_pll,
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# 62.5MHz: 1/4 PCLK
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p_CLKOUT2_DIVIDE=16, p_CLKOUT2_PHASE=0.0,
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o_CLKOUT2=phy_pipe_quarter_clk_pll,
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# 250Mhz: TX CLK, phase shift 90
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p_CLKOUT3_DIVIDE=4, p_CLKOUT3_PHASE=90.0,
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o_CLKOUT3=phy_pipe_tx_clk_phase_pll
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),
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Instance("BUFG", i_I=phy_pipe_half_clk_pll, o_O=phy_pipe_half_clk),
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Instance("BUFG", i_I=phy_pipe_half_clk_phase_pll, o_O=phy_pipe_half_clk_phase),
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Instance("BUFG", i_I=phy_pipe_quarter_clk_pll, o_O=phy_pipe_quarter_clk),
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Instance("BUFG", i_I=phy_pipe_tx_clk_phase_pll, o_O=phy_pipe_tx_clk_phase),
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]
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self.clock_domains.cd_phy_pipe_half = ClockDomain()
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self.clock_domains.cd_phy_pipe_half_phase = ClockDomain()
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self.clock_domains.cd_phy_pipe_quarter = ClockDomain()
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self.clock_domains.cd_phy_pipe_tx_phase = ClockDomain()
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self.comb += [
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self.cd_phy_pipe_half.clk.eq(phy_pipe_half_clk),
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self.cd_phy_pipe_half_phase.clk.eq(phy_pipe_half_clk_phase),
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self.cd_phy_pipe_quarter.clk.eq(phy_pipe_quarter_clk),
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self.cd_phy_pipe_tx_phase.clk.eq(phy_pipe_tx_clk_phase)
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]
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self.specials += [
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AsyncResetSynchronizer(self.cd_phy_pipe_half, ~phy_pipe_pll_locked),
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AsyncResetSynchronizer(self.cd_phy_pipe_half_phase, ~phy_pipe_pll_locked),
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AsyncResetSynchronizer(self.cd_phy_pipe_quarter, ~phy_pipe_pll_locked),
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AsyncResetSynchronizer(self.cd_phy_pipe_tx_phase, ~phy_pipe_pll_locked)
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]
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self.cd_phy_pipe_half.clk.attr.add("keep")
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self.cd_phy_pipe_half_phase.clk.attr.add("keep")
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self.cd_phy_pipe_quarter.clk.attr.add("keep")
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self.cd_phy_pipe_tx_phase.clk.attr.add("keep")
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self.platform.add_period_constraint(self.cd_phy_pipe_half.clk, 8.0)
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self.platform.add_period_constraint(self.cd_phy_pipe_half_phase.clk, 8.0)
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self.platform.add_period_constraint(self.cd_phy_pipe_quarter.clk, 16.0)
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self.platform.add_period_constraint(self.cd_phy_pipe_tx_phase.clk, 4.0)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.cd_phy_pipe_half.clk,
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self.cd_phy_pipe_half_phase.clk,
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self.cd_phy_pipe_quarter.clk,
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self.cd_phy_pipe_tx_phase.clk)
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phy_pipe_rx_data = Signal(32)
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phy_pipe_rx_datak = Signal(4)
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phy_pipe_rx_valid = Signal(2)
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phy_pipe_tx_data = Signal(32)
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phy_pipe_tx_datak = Signal(4)
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phy_rx_status = Signal(6)
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phy_phy_status = Signal(2)
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dbg_pipe_state = Signal(6)
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dbg_ltssm_state = Signal(5)
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usb_pipe_status_phy_status = Signal()
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self.specials += Tristate(usb_pipe_status.phy_status, 0, ~usb3_reset_n, usb_pipe_status_phy_status)
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self.comb += usb3_reset_n.eq(self.usb3_control.phy_enable)
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self.specials += Instance("usb3_top",
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i_ext_clk = ClockSignal(),
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i_reset_n = self.usb3_control.core_enable,
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i_phy_pipe_half_clk = ClockSignal("phy_pipe_half"),
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i_phy_pipe_half_clk_phase = ClockSignal("phy_pipe_half_phase"),
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i_phy_pipe_quarter_clk = ClockSignal("phy_pipe_quarter"),
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i_phy_pipe_rx_data = phy_pipe_rx_data,
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i_phy_pipe_rx_datak = phy_pipe_rx_datak,
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i_phy_pipe_rx_valid = phy_pipe_rx_valid,
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o_phy_pipe_tx_data = phy_pipe_tx_data,
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o_phy_pipe_tx_datak = phy_pipe_tx_datak,
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#o_phy_reset_n = ,
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#o_phy_out_enable = ,
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o_phy_phy_reset_n = usb_pipe_ctrl.phy_reset_n,
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o_phy_tx_detrx_lpbk = usb_pipe_ctrl.tx_detrx_lpbk,
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o_phy_tx_elecidle = usb_pipe_ctrl.tx_elecidle,
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io_phy_rx_elecidle = usb_pipe_status.rx_elecidle,
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i_phy_rx_status = phy_rx_status,
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o_phy_power_down = usb_pipe_ctrl.power_down,
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i_phy_phy_status_i = phy_phy_status,
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#o_phy_phy_status_o = ,
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i_phy_pwrpresent = usb_pipe_status.pwr_present,
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o_phy_tx_oneszeros = usb_pipe_ctrl.tx_oneszeros,
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o_phy_tx_deemph = usb_pipe_ctrl.tx_deemph,
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o_phy_tx_margin = usb_pipe_ctrl.tx_margin,
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o_phy_tx_swing = usb_pipe_ctrl.tx_swing,
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o_phy_rx_polarity = usb_pipe_ctrl.rx_polarity,
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o_phy_rx_termination = usb_pipe_ctrl.rx_termination,
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o_phy_rate = usb_pipe_ctrl.rate,
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o_phy_elas_buf_mode = usb_pipe_ctrl.elas_buf_mode,
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i_buf_in_addr = self.usb3_control.buf_in_addr,
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i_buf_in_data = self.usb3_control.buf_in_data,
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i_buf_in_wren = self.usb3_control.buf_in_wren,
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o_buf_in_request = self.usb3_control.buf_in_request,
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o_buf_in_ready = self.usb3_control.buf_in_ready,
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i_buf_in_commit = self.usb3_control.buf_in_commit,
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i_buf_in_commit_len = self.usb3_control.buf_in_commit_len,
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o_buf_in_commit_ack = self.usb3_control.buf_in_commit_ack,
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i_buf_out_addr = self.usb3_control.buf_out_addr,
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o_buf_out_q = self.usb3_control.buf_out_q,
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o_buf_out_len = self.usb3_control.buf_out_len,
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o_buf_out_hasdata = self.usb3_control.buf_out_hasdata,
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i_buf_out_arm = self.usb3_control.buf_out_arm,
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o_buf_out_arm_ack = self.usb3_control.buf_out_arm_ack,
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#o_vend_req_act =,
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#o_vend_req_request =,
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#o_vend_req_val =,
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o_dbg_pipe_state = dbg_pipe_state,
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o_dbg_ltssm_state = dbg_ltssm_state
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)
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platform.add_verilog_include_path(os.path.join("core"))
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platform.add_verilog_include_path(os.path.join("core", "usb3"))
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platform.add_source_dir(os.path.join("core", "usb3"))
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# ddr inputs
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self.specials += Instance("IDDR",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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i_C=ClockSignal("phy_pipe_half"), i_CE=1, i_S=0, i_R=0,
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i_D=usb_pipe_data.rx_valid, o_Q1=phy_pipe_rx_valid[0], o_Q2=phy_pipe_rx_valid[1],
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)
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for i in range(16):
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self.specials += Instance("IDDR",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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i_C=ClockSignal("phy_pipe_half"), i_CE=1, i_S=0, i_R=0,
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i_D=usb_pipe_data.rx_data[i], o_Q1=phy_pipe_rx_data[i], o_Q2=phy_pipe_rx_data[16+i],
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)
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for i in range(2):
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self.specials += Instance("IDDR",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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i_C=ClockSignal("phy_pipe_half"), i_CE=1, i_S=0, i_R=0,
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i_D=usb_pipe_data.rx_datak[i], o_Q1=phy_pipe_rx_datak[i], o_Q2=phy_pipe_rx_datak[2+i],
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)
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for i in range(3):
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self.specials += Instance("IDDR",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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i_C=ClockSignal("phy_pipe_half"), i_CE=1, i_S=0, i_R=0,
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i_D=usb_pipe_status.rx_status[i], o_Q1=phy_rx_status[i], o_Q2=phy_rx_status[3+i],
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)
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self.specials += Instance("IDDR",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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i_C=ClockSignal("phy_pipe_half"), i_CE=1, i_S=0, i_R=0,
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i_D=usb_pipe_status_phy_status, o_Q1=phy_phy_status[0], o_Q2=phy_phy_status[1],
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)
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# ddr outputs
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self.specials += Instance("ODDR",
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p_DDR_CLK_EDGE="SAME_EDGE",
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i_C=ClockSignal("phy_pipe_tx_phase"), i_CE=1, i_S=0, i_R=0,
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i_D1=1, i_D2=0, o_Q=usb_pipe_data.tx_clk,
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)
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for i in range(16):
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self.specials += Instance("ODDR",
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p_DDR_CLK_EDGE="SAME_EDGE",
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i_C=ClockSignal("phy_pipe_half_phase"), i_CE=1, i_S=0, i_R=0,
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i_D1=phy_pipe_tx_data[i], i_D2=phy_pipe_tx_data[16+i], o_Q=usb_pipe_data.tx_data[i],
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)
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for i in range(2):
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self.specials += Instance("ODDR",
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p_DDR_CLK_EDGE="SAME_EDGE",
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i_C=ClockSignal("phy_pipe_half_phase"), i_CE=1, i_S=0, i_R=0,
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i_D1=phy_pipe_tx_datak[i], i_D2=phy_pipe_tx_datak[2+i], o_Q=usb_pipe_data.tx_datak[i],
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)
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