mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
92 lines
2.6 KiB
Python
Executable File
92 lines
2.6 KiB
Python
Executable File
#!/usr/bin/env python3
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import sys
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import time
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from litex import RemoteClient
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from litescope import LiteScopeAnalyzerDriver
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wb = RemoteClient()
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wb.open()
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# # #
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def help():
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print("Supported triggers:")
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print(" - rx_polling")
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print(" - tx_polling")
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print("")
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print(" - rx_tseq_first_word")
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print(" - rx_tseq")
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print(" - rx_ts1")
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print(" - rx_ts2")
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print(" - tx_ts2")
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print("")
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print(" - ready")
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print(" - skip")
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print("")
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print(" - sink_ready")
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print(" - source_valid")
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print("")
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print(" - now")
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exit()
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if len(sys.argv) < 2:
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help()
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if len(sys.argv) < 3:
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length = 4096
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else:
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length = int(sys.argv[2])
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# FPGA ID ------------------------------------------------------------------------------------------
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fpga_id = ""
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for i in range(256):
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c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
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fpga_id += c
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if c == "\0":
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break
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print("FPGA: " + fpga_id)
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# Analyzer dump ------------------------------------------------------------------------------------
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analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
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if sys.argv[1] == "rx_polling":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_rx_polling")
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elif sys.argv[1] == "tx_polling":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_tx_polling")
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elif sys.argv[1] == "rx_tseq_first_word":
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from usb3_pipe.common import TSEQ
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TSEQ_FIRST_WORD = int.from_bytes(TSEQ.to_bytes()[0:4], byteorder="little")
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analyzer.configure_trigger(cond={
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"soc_usb3_serdes_source_source_valid" : 1,
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"soc_usb3_serdes_source_source_payload_data": TSEQ_FIRST_WORD})
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elif sys.argv[1] == "rx_tseq":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_rx_tseq")
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elif sys.argv[1] == "rx_ts1":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_rx_ts1")
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elif sys.argv[1] == "rx_ts2":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_rx_ts2")
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elif sys.argv[1] == "tx_ts2":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_tx_ts2")
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elif sys.argv[1] == "ready":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_ready")
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elif sys.argv[1] == "skip":
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analyzer.add_rising_edge_trigger("soc_usb3_serdes_rx_skip")
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elif sys.argv[1] == "sink_ready":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_sink_ready")
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elif sys.argv[1] == "source_valid":
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analyzer.add_rising_edge_trigger("soc_usb3_pipe_source_valid")
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elif sys.argv[1] == "now":
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analyzer.configure_trigger(cond={})
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else:
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raise ValueError
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analyzer.configure_trigger(cond={})
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analyzer.run(offset=32, length=length)
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analyzer.wait_done()
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analyzer.upload()
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analyzer.save("analyzer.vcd")
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# # #
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wb.close()
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