High Speed Transceiver PIPE Wrapper Experiments
The aim of this project is to experiment with High Speed Transceivers (SERDES) of popular FPGAs to create a USB3.0 PIPE interface.
Targets
While we hope this wrapper will eventually support multiple protocols through the PIPE interface (such as PCIe, SATA, DisplayPort) it is currently targetting support for USB3.0 SuperSpeed when used with a customized the Daisho USB3 core.
It currently targets the following FPGA parts;
- Xilinx Kintex 7
- Lattice ECP5-5G
It is hoped to eventually expand the support beyond these initial parts to;
- Xilinx Artix 7
- Xilinx Ultrascale/Ultrascale+ line
- Various Xilinx Zynq line
- Altera Cyclone parts
Test Hardware
One of the following boards;
paired with
These boards have been previously shown to work with the Daisho Core and the TI TUSB1310A - SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces.
Toolchain
This project targets;
- Xilinx Vivado for Kintex 7 support
- Yosys + nextpnr for ECP5 support
There will also be a demo showing how to use a harness to expose the PIPE interface to the SymbiFlow Yosys + VPR flow.