mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
285 lines
11 KiB
Python
Executable File
285 lines
11 KiB
Python
Executable File
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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#!/usr/bin/env python3
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from migen import *
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from migen.genlib.misc import WaitTimer
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.uart import UARTWishboneBridge
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from litex.boards.platforms import nexys_video
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from litescope import LiteScopeAnalyzer
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from usb3_pipe.common import TSEQ, TS1, TS2
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from usb3_pipe.serdes import A7USB3SerDes
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from usb3_pipe.scrambler import Scrambler
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from usb3_pipe.lfps import LFPSChecker, LFPSGenerator
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from usb3_pipe.ordered_set import OrderedSetChecker, OrderedSetGenerator
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("AB1"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AB8"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("AA1"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("AB6"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("T1")),
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Subsignal("rx", Pins("U1")),
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IOStandard("LVCMOS33"),
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),
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("pcie_tx", 0,
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Subsignal("p", Pins("B6")),
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Subsignal("n", Pins("A6")),
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),
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("pcie_rx", 0,
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Subsignal("p", Pins("B10")),
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Subsignal("n", Pins("A10")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_oob = ClockDomain()
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self.clock_domains.cd_clk125 = ClockDomain()
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# # #
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 1e9/100e6)
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self.cd_sys.clk.attr.add("keep")
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self.cd_clk125.clk.attr.add("keep")
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self.submodules.pll = pll = S7PLL(speedgrade=-2)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_oob, sys_clk_freq/8)
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pll.create_clkout(self.cd_clk125, 125e6)
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# USB3SoC ------------------------------------------------------------------------------------------
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class USB3SoC(SoCMini):
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def __init__(self, platform,
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with_lfps_analyzer=False,
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with_rx_analyzer=True,
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with_tx_analyzer=True,
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with_fsm_analyzer=True):
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sys_clk_freq = int(100e6)
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SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Serial bridge ----------------------------------------------------------------------------
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self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
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self.add_wb_master(self.serial_bridge.wishbone)
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# USB3 SerDes ------------------------------------------------------------------------------
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usb3_serdes = A7USB3SerDes(platform,
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sys_clk = self.crg.cd_sys.clk,
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sys_clk_freq = sys_clk_freq,
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refclk_pads = ClockSignal("clk125"),
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refclk_freq = 125e6,
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tx_pads = platform.request("pcie_tx"),
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rx_pads = platform.request("pcie_rx"))
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self.submodules += usb3_serdes
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
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# LFPS Polling Receive ---------------------------------------------------------------------
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lfps_receiver = LFPSChecker(sys_clk_freq=sys_clk_freq)
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self.submodules += lfps_receiver
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self.comb += lfps_receiver.idle.eq(usb3_serdes.rx_idle)
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# LFPS Polling Transmit --------------------------------------------------------------------
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lfps_transmitter = LFPSGenerator(sys_clk_freq=sys_clk_freq, lfps_clk_freq=25e6)
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self.submodules += lfps_transmitter
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self.comb += [
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If(lfps_transmitter.polling,
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usb3_serdes.tx_idle.eq(lfps_transmitter.tx_idle),
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usb3_serdes.tx_pattern.eq(lfps_transmitter.tx_pattern)
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).Else(
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usb3_serdes.tx_idle.eq(0)
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)
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]
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# TSEQ Receiver ----------------------------------------------------------------------------
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tseq_receiver = OrderedSetChecker(ordered_set=TSEQ, n_ordered_sets=1024, data_width=32)
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tseq_receiver = ClockDomainsRenamer("rx")(tseq_receiver)
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self.submodules += tseq_receiver
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# TS1 Receiver -----------------------------------------------------------------------------
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ts1_receiver = OrderedSetChecker(ordered_set=TS1, n_ordered_sets=16, data_width=32)
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ts1_receiver = ClockDomainsRenamer("rx")(ts1_receiver)
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self.submodules += ts1_receiver
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# TS2 Receiver -----------------------------------------------------------------------------
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ts2_receiver = OrderedSetChecker(ordered_set=TS2, n_ordered_sets=1024, data_width=32)
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ts2_receiver = ClockDomainsRenamer("rx")(ts2_receiver)
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self.submodules += ts2_receiver
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# TS2 Transmitter --------------------------------------------------------------------------
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ts2_transmitter = OrderedSetGenerator(ordered_set=TS2, n_ordered_sets=1024, data_width=32)
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ts2_transmitter = ClockDomainsRenamer("tx")(ts2_transmitter)
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self.submodules += ts2_transmitter
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# Scrambler --------------------------------------------------------------------------------
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scrambler = Scrambler()
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scrambler = ClockDomainsRenamer("tx")(scrambler)
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self.submodules += scrambler
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# Hacky Startup FSM (just to experiment on hardware) ---------------------------------------
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tseq_det_sync = PulseSynchronizer("rx", "tx")
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ts1_det_sync = PulseSynchronizer("rx", "tx")
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ts2_det_sync = PulseSynchronizer("rx", "tx")
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self.submodules += tseq_det_sync, ts1_det_sync, ts2_det_sync
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self.comb += [
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tseq_det_sync.i.eq(tseq_receiver.detected),
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ts1_det_sync.i.eq(ts1_receiver.detected),
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ts2_det_sync.i.eq(ts2_receiver.detected),
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]
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fsm = FSM(reset_state="POLLING-LFPS")
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fsm = ClockDomainsRenamer("tx")(fsm)
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fsm = ResetInserter()(fsm)
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self.submodules += fsm
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self.comb += fsm.reset.eq(lfps_receiver.polling)
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fsm.act("POLLING-LFPS",
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scrambler.reset.eq(1),
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usb3_serdes.rx_align.eq(1),
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lfps_transmitter.polling.eq(1),
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NextValue(ts2_transmitter.send, 0),
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NextState("WAIT-TSEQ"),
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)
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fsm.act("WAIT-TSEQ",
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usb3_serdes.rx_align.eq(1),
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lfps_transmitter.polling.eq(1),
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usb3_serdes.source.connect(tseq_receiver.sink),
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If(tseq_det_sync.o,
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NextState("SEND-POLLING-LFPS-WAIT-TS1")
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)
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)
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fsm.act("SEND-POLLING-LFPS-WAIT-TS1",
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usb3_serdes.rx_align.eq(0),
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usb3_serdes.source.connect(ts1_receiver.sink),
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If(ts1_det_sync.o,
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NextValue(ts2_transmitter.send, 1),
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NextState("SEND-TS2-WAIT-TS2")
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)
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)
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ts2_det = Signal()
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fsm.act("SEND-TS2-WAIT-TS2",
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usb3_serdes.rx_align.eq(0),
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usb3_serdes.source.connect(ts2_receiver.sink),
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ts2_transmitter.source.connect(usb3_serdes.sink),
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NextValue(ts2_det, ts2_det | ts2_det_sync.o),
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NextValue(ts2_transmitter.send, 0),
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If(ts2_transmitter.done,
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If(ts2_det,
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NextState("READY")
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).Else(
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NextValue(ts2_transmitter.send, 1)
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)
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)
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)
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fsm.act("READY",
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usb3_serdes.rx_align.eq(0),
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scrambler.sink.valid.eq(1),
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scrambler.source.connect(usb3_serdes.sink),
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)
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# Leds -------------------------------------------------------------------------------------
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self.comb += platform.request("user_led", 0).eq(usb3_serdes.gtp.tx_ready & usb3_serdes.gtp.rx_ready)
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self.comb += platform.request("user_led", 1).eq(usb3_serdes.rx_idle)
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# LFPS Analyzer ----------------------------------------------------------------------------
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if with_lfps_analyzer:
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analyzer_signals = [
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rxelecidle,
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txelecidle,
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lfps_receiver.polling,
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lfps_receiver.count,
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lfps_receiver.found,
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lfps_receiver.fsm,
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]
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self.submodules.lfps_analyzer = LiteScopeAnalyzer(analyzer_signals, 32768, clock_domain="sys", csr_csv="lfps_analyzer.csv")
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self.add_csr("lfps_analyzer")
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# RX Analyzer ------------------------------------------------------------------------------
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if with_rx_analyzer:
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analyzer_signals = [
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fsm,
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usb3_serdes.source,
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tseq_receiver.detected,
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ts1_receiver.detected,
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ts1_receiver.reset,
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ts1_receiver.loopback,
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ts1_receiver.scrambling,
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ts2_receiver.detected,
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ts2_receiver.reset,
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ts2_receiver.loopback,
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ts2_receiver.scrambling
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]
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self.submodules.rx_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="rx", csr_csv="rx_analyzer.csv")
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self.add_csr("rx_analyzer")
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# TX Analyzer ------------------------------------------------------------------------------
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if with_tx_analyzer:
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analyzer_signals = [
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fsm,
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usb3_serdes.sink,
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ts2_transmitter.send,
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ts2_transmitter.done,
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]
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self.submodules.tx_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="tx", csr_csv="tx_analyzer.csv")
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self.add_csr("tx_analyzer")
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# FSM Analyzer -----------------------------------------------------------------------------
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if with_fsm_analyzer:
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analyzer_signals = [
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fsm,
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tseq_det_sync.o,
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ts1_det_sync.o,
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ts2_det_sync.o,
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]
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self.submodules.fsm_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="sys", csr_csv="fsm_analyzer.csv")
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self.add_csr("fsm_analyzer")
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# Build --------------------------------------------------------------------------------------------
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def main():
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platform = Platform()
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soc = USB3SoC(platform)
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builder = Builder(soc, output_dir="build", csr_csv="csr.csv")
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vns = builder.build()
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if __name__ == "__main__":
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main()
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