mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
58 lines
1.7 KiB
Python
Executable File
58 lines
1.7 KiB
Python
Executable File
#!/usr/bin/env python3
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import sys
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import time
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from litex import RemoteClient
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from litescope import LiteScopeAnalyzerDriver
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from usb3_pipe.common import TSEQ, TS1, TS2
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wb = RemoteClient()
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wb.open()
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# # #
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TSEQ_FIRST_WORD = int.from_bytes(TSEQ.to_bytes()[0:4], byteorder="little")
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TS1_FIRST_WORD = int.from_bytes(TS1.to_bytes()[0:4], byteorder="little")
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# FPGA ID ------------------------------------------------------------------------------------------
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fpga_id = ""
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for i in range(256):
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c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
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fpga_id += c
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if c == "\0":
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break
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print("FPGA: " + fpga_id)
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# Enable Capture -----------------------------------------------------------------------------------
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wb.regs.gtx_rx_polarity.write(1)
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wb.regs.gtx_tx_enable.write(1)
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while (wb.regs.gtx_tx_ready.read() == 0):
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pass
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wb.regs.gtx_rx_enable.write(1)
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while (wb.regs.gtx_rx_ready.read() == 0):
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pass
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# Analyzer dump ------------------------------------------------------------------------------------
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analyzer = LiteScopeAnalyzerDriver(wb.regs, "rx_analyzer", debug=True)
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analyzer.configure_subsampler(1)
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#analyzer.configure_trigger(cond={
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# "soc_gtx0_source_payload_ctrl": 0b0001,
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# "soc_gtx0_source_payload_data": TSEQ_FIRST_WORD})
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#analyzer.configure_trigger(cond={
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# "soc_gtx0_source_payload_ctrl": 0b1111,
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# "soc_gtx0_source_payload_data": TS1_FIRST_WORD})
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#analyzer.configure_trigger(cond={"soc_tseq_receiver_detected": 1})
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#analyzer.configure_trigger(cond={"soc_ts1_receiver_detected": 1})
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#analyzer.configure_trigger(cond={"soc_ts2_receiver_detected": 1})
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analyzer.configure_trigger(cond={})
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analyzer.run(offset=32, length=4096)
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analyzer.wait_done()
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analyzer.upload()
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analyzer.save("analyzer.vcd")
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# # #
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wb.close()
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