FPGA/usbcorev
1
0
Fork 0
mirror of https://github.com/avakar/usbcorev.git synced 2024-10-22 02:17:39 +08:00
Code Issues Projects Releases Wiki Activity

Transmitter is now able to send the sequence FE:01:01.

Browse Source
This commit is contained in:
Martin Vejnár 2013-07-28 10:22:37 +02:00
parent ffdeaa1b4d
commit 7ee18812df
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
usb_tx.v
View File

@ -48,7 +48,7 @@ wire d = dump_crc? !crc_out: tx_data[0];
wire se0 = !bit_stuff && (state == st_eop1 || state == st_eop2); wire se0 = !bit_stuff && (state == st_eop1 || state == st_eop2);
wire tx_data_empty = (tx_data[8:2] == 1'b0); wire tx_data_empty = (tx_data[8:2] == 1'b0);
assign data_strobe = transmit && tx_data_empty && bit_strobe; assign data_strobe = transmit && tx_data_empty && tx_strobe;
always @(posedge clk_48 or negedge rst_n) begin always @(posedge clk_48 or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin