FPGA/usbcorev
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3 Commits

Author SHA1 Message Date
Martin Vejnár
a44dc24dd0 No more vendor specific components. 
Input and output is now done via design-treated j/se0 signals;
it is up to the design to tread input for metastability.
 2013-07-05 18:01:04 +02:00
Martin Vejnár
ee47046404 Fixed ACK timing on toggle error. 2013-06-09 10:54:03 +02:00
Martin Vejnár
fb2e32dc58 Initial commit. 
The module works correctly during USB enumeration, no more tests were
performed at this point. No documentation or tests.
 2013-05-10 19:51:51 +02:00