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82 lines
2.8 KiB
Markdown
82 lines
2.8 KiB
Markdown
This core allows you to embed a full-speed (12Mbps) USB 2.0 device core into your FPGA design.
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## Clocks
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The core requires a reasonably precise 48MHz clock. You'd better derive it from a crystal oscillator.
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## Physical interface
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Since USB uses a bit of a weird signaling on its half-duplex (almost-)differential line,
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you'll, need to do a little bit of work to connect it to the core. The following five signals
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connect to D+ and D- USB signals.
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* `input rx_j` -- the differential value on D+/D- lines
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* `input rx_se0` -- single-ended zero detected: should be set when both D+ and D- lines are zero
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* `output tx_se0` -- transmit zeros on both USB lines; has priority over `tx_j`
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* `output tx_j` -- transmit `tx_j` to D+ and `~tx_j` to D-
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* `output tx_en` -- enable the trasmitter
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If your FPGA doesn't have a differential receiver, then you can simply use two pins and connect them as follows.
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However, without a differential receiver, you will be outside of the USB specs.
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Make sure the inputs are synchronized to the USB clock.
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inout usb_dp;
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inout usb_dn;
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// ...
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wire usb_tx_se0, usb_tx_j, usb_tx_en;
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usb usb0(
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.rx_j(usb_dp),
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.rx_se0(!usb_dp && !usb_dn),
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.tx_se0(usb_tx_se0),
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.tx_j(usb_tx_j),
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.tx_en(usb_tx_en));
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assign usb_dp = usb_tx_en? (usb_tx_se0? 1'b0: usb_tx_j): 1'bz;
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assign usb_dn = usb_tx_en? (usb_tx_se0? 1'b0: !usb_tx_j): 1'bz;
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However, if you have a differential receiver, you'd better use it. Configuring this is FPGA-specific.
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For Xilinx Spartan 6 family, I use four physical pins as follows.
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// These pins are configured as differential inputs. Unfortunately,
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// you can't use single-ended receivers nor transmitters on these pins.
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input usb_sp;
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input usb_sn;
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// These pins are single-ended inouts.
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inout usb_dp;
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inout usb_dn'
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// ...
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IBUFDS usb_j_buf(.I(usb_sp), .IB(usb_sn), .O(usb_rx_j_presync));
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synch usb_j_synch(clk_48, usb_rx_j_presync, usb_rx_j);
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synch usb_se0_synch(clk_48, !usb_dp && !usb_dn, usb_rx_se0);
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wire usb_tx_se0, usb_tx_j, usb_tx_en;
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usb usb0(
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.rx_j(usb_rx_j),
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.rx_se0(usb_rx_se0),
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.tx_se0(usb_tx_se0),
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.tx_j(usb_tx_j),
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.tx_en(usb_tx_en));
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assign usb_dp = usb_tx_en? (usb_tx_se0? 1'b0: usb_tx_j): 1'bz;
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assign usb_dn = usb_tx_en? (usb_tx_se0? 1'b0: !usb_tx_j): 1'bz;
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Note the synchronization after the receiver.
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Whichever pins you transmit on need to have resistors after them.
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The exact values will depend on the internal resistance of the pins;
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usually something around 27 ohms will be ok.
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You also need to pull the D+ line up to 3.3V via a 1.5k resistor.
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You can pull it directly, or via a pin on your FPGA, if you want to
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dynamically attach/detach to the bus.
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Make sure to never pull the line down, the only valid outputs
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of the pullup pin are `1'b1` and `1'bz`.
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