Martin Vejnár 630f5ea125 Add license.

2017-12-15 09:38:04 +01:00

crc5.py

Initial commit.

2013-05-10 19:51:51 +02:00

crc16.py

Initial commit.

2013-05-10 19:51:51 +02:00

LICENSE

Add license.

2017-12-15 09:38:04 +01:00

usb_ep_banked.v

Added a banked ep.

2014-09-07 17:40:57 +02:00

usb_ep.v

Changed usb_ep interface.

2014-09-07 14:16:59 +02:00

usb_recv.v

No more vendor specific components.

2013-07-05 18:01:04 +02:00

usb_tx.v

Transmitter is now able to send the sequence FE:01:01.

2013-07-28 10:22:37 +02:00

usb_utils.v

Initial commit.

2013-05-10 19:51:51 +02:00

usb.v

Fixed handshake race.

2014-09-07 00:24:18 +02:00

utils.v

Removed sync as it is no longer used.

2013-07-05 18:04:31 +02:00

Description

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fpgausbverilog

46 KiB

Languages

Verilog 98.4%

Python 1.6%