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Use correct wait

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Alex Forencich 2019-02-01 17:28:22 -08:00
parent 787f198970
commit 199a5544ca
1 changed files with 1 additions and 1 deletions
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2
tb/test_axil_dp_ram.py
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@ -403,7 +403,7 @@ def bench():
axil_b_master_inst.init_write(k*256, b'\x11\x22\x33\x44')
axil_b_master_inst.init_read(k*256, 4)
yield wait()
yield wait_normal()
for k in range(10):
axil_a_master_inst.get_read_data()