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Add simple register as a per-channel option to AXI register modules

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Alex Forencich 2018-08-16 13:25:07 -07:00
parent d541c64bc0
commit 48577f3a2d
9 changed files with 387 additions and 50 deletions
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20
rtl/axi_register.v
View File

@ -45,11 +45,11 @@ module axi_register #
parameter ARUSER_WIDTH = 1, parameter ARUSER_WIDTH = 1,
parameter RUSER_ENABLE = 0, parameter RUSER_ENABLE = 0,
parameter RUSER_WIDTH = 1, parameter RUSER_WIDTH = 1,
parameter AW_REG_ENABLE = 1, parameter AW_REG_TYPE = 1,
parameter W_REG_ENABLE = 1, parameter W_REG_TYPE = 2,
parameter B_REG_ENABLE = 1, parameter B_REG_TYPE = 1,
parameter AR_REG_ENABLE = 1, parameter AR_REG_TYPE = 1,
parameter R_REG_ENABLE = 1 parameter R_REG_TYPE = 2
) )
( (
input wire clk, input wire clk,
@ -163,9 +163,9 @@ axi_register_wr #(
.WUSER_WIDTH(WUSER_WIDTH), .WUSER_WIDTH(WUSER_WIDTH),
.BUSER_ENABLE(BUSER_ENABLE), .BUSER_ENABLE(BUSER_ENABLE),
.BUSER_WIDTH(BUSER_WIDTH), .BUSER_WIDTH(BUSER_WIDTH),
.AW_REG_ENABLE(AW_REG_ENABLE), .AW_REG_TYPE(AW_REG_TYPE),
.W_REG_ENABLE(W_REG_ENABLE), .W_REG_TYPE(W_REG_TYPE),
.B_REG_ENABLE(B_REG_ENABLE) .B_REG_TYPE(B_REG_TYPE)
) )
axi_register_wr_inst ( axi_register_wr_inst (
.clk(clk), .clk(clk),
@ -237,8 +237,8 @@ axi_register_rd #(
.ARUSER_WIDTH(ARUSER_WIDTH), .ARUSER_WIDTH(ARUSER_WIDTH),
.RUSER_ENABLE(RUSER_ENABLE), .RUSER_ENABLE(RUSER_ENABLE),
.RUSER_WIDTH(RUSER_WIDTH), .RUSER_WIDTH(RUSER_WIDTH),
.AR_REG_ENABLE(AR_REG_ENABLE), .AR_REG_TYPE(AR_REG_TYPE),
.R_REG_ENABLE(R_REG_ENABLE) .R_REG_TYPE(R_REG_TYPE)
) )
axi_register_rd_inst ( axi_register_rd_inst (
.clk(clk), .clk(clk),

150
rtl/axi_register_rd.v
View File

@ -39,8 +39,8 @@ module axi_register_rd #
parameter ARUSER_WIDTH = 1, parameter ARUSER_WIDTH = 1,
parameter RUSER_ENABLE = 0, parameter RUSER_ENABLE = 0,
parameter RUSER_WIDTH = 1, parameter RUSER_WIDTH = 1,
parameter AR_REG_ENABLE = 1, parameter AR_REG_TYPE = 1,
parameter R_REG_ENABLE = 1 parameter R_REG_TYPE = 2
) )
( (
input wire clk, input wire clk,
@ -99,7 +99,8 @@ generate
// AR channel // AR channel
if (AR_REG_ENABLE) begin if (AR_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers // datapath registers
reg s_axi_arready_reg = 1'b0; reg s_axi_arready_reg = 1'b0;
@ -234,6 +235,85 @@ always @(posedge clk) begin
end end
end end
end else if (AR_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg s_axi_arready_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};
reg [7:0] m_axi_arlen_reg = 8'd0;
reg [2:0] m_axi_arsize_reg = 3'd0;
reg [1:0] m_axi_arburst_reg = 2'd0;
reg m_axi_arlock_reg = 1'b0;
reg [3:0] m_axi_arcache_reg = 4'd0;
reg [2:0] m_axi_arprot_reg = 3'd0;
reg [3:0] m_axi_arqos_reg = 4'd0;
reg [3:0] m_axi_arregion_reg = 4'd0;
reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};
reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
// datapath control
reg store_axi_ar_input_to_output;
assign s_axi_arready = s_axi_arready_reg;
assign m_axi_arid = m_axi_arid_reg;
assign m_axi_araddr = m_axi_araddr_reg;
assign m_axi_arlen = m_axi_arlen_reg;
assign m_axi_arsize = m_axi_arsize_reg;
assign m_axi_arburst = m_axi_arburst_reg;
assign m_axi_arlock = m_axi_arlock_reg;
assign m_axi_arcache = m_axi_arcache_reg;
assign m_axi_arprot = m_axi_arprot_reg;
assign m_axi_arqos = m_axi_arqos_reg;
assign m_axi_arregion = m_axi_arregion_reg;
assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};
assign m_axi_arvalid = m_axi_arvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axi_arready_early = !m_axi_arvalid_next;
always @* begin
// transfer sink ready state to source
m_axi_arvalid_next = m_axi_arvalid_reg;
store_axi_ar_input_to_output = 1'b0;
if (s_axi_arready_reg) begin
m_axi_arvalid_next = s_axi_arvalid;
store_axi_ar_input_to_output = 1'b1;
end else if (m_axi_arready) begin
m_axi_arvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
s_axi_arready_reg <= 1'b0;
m_axi_arvalid_reg <= 1'b0;
end else begin
s_axi_arready_reg <= s_axi_arready_early;
m_axi_arvalid_reg <= m_axi_arvalid_next;
end
// datapath
if (store_axi_ar_input_to_output) begin
m_axi_arid_reg <= s_axi_arid;
m_axi_araddr_reg <= s_axi_araddr;
m_axi_arlen_reg <= s_axi_arlen;
m_axi_arsize_reg <= s_axi_arsize;
m_axi_arburst_reg <= s_axi_arburst;
m_axi_arlock_reg <= s_axi_arlock;
m_axi_arcache_reg <= s_axi_arcache;
m_axi_arprot_reg <= s_axi_arprot;
m_axi_arqos_reg <= s_axi_arqos;
m_axi_arregion_reg <= s_axi_arregion;
m_axi_aruser_reg <= s_axi_aruser;
end
end
end else begin end else begin
// bypass AR channel // bypass AR channel
@ -255,7 +335,8 @@ end
// R channel // R channel
if (R_REG_ENABLE) begin if (R_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers // datapath registers
reg m_axi_rready_reg = 1'b0; reg m_axi_rready_reg = 1'b0;
@ -354,6 +435,67 @@ always @(posedge clk) begin
end end
end end
end else if (R_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg m_axi_rready_reg = 1'b0;
reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}};
reg [1:0] s_axi_rresp_reg = 2'b0;
reg s_axi_rlast_reg = 1'b0;
reg [RUSER_WIDTH-1:0] s_axi_ruser_reg = {RUSER_WIDTH{1'b0}};
reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
// datapath control
reg store_axi_r_input_to_output;
assign m_axi_rready = m_axi_rready_reg;
assign s_axi_rid = s_axi_rid_reg;
assign s_axi_rdata = s_axi_rdata_reg;
assign s_axi_rresp = s_axi_rresp_reg;
assign s_axi_rlast = s_axi_rlast_reg;
assign s_axi_ruser = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}};
assign s_axi_rvalid = s_axi_rvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire m_axi_rready_early = !s_axi_rvalid_next;
always @* begin
// transfer sink ready state to source
s_axi_rvalid_next = s_axi_rvalid_reg;
store_axi_r_input_to_output = 1'b0;
if (m_axi_rready_reg) begin
s_axi_rvalid_next = m_axi_rvalid;
store_axi_r_input_to_output = 1'b1;
end else if (s_axi_rready) begin
s_axi_rvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
m_axi_rready_reg <= 1'b0;
s_axi_rvalid_reg <= 1'b0;
end else begin
m_axi_rready_reg <= m_axi_rready_early;
s_axi_rvalid_reg <= s_axi_rvalid_next;
end
// datapath
if (store_axi_r_input_to_output) begin
s_axi_rid_reg <= m_axi_rid;
s_axi_rdata_reg <= m_axi_rdata;
s_axi_rresp_reg <= m_axi_rresp;
s_axi_rlast_reg <= m_axi_rlast;
s_axi_ruser_reg <= m_axi_ruser;
end
end
end else begin end else begin
// bypass R channel // bypass R channel

207
rtl/axi_register_wr.v
View File

@ -41,9 +41,9 @@ module axi_register_wr #
parameter WUSER_WIDTH = 1, parameter WUSER_WIDTH = 1,
parameter BUSER_ENABLE = 0, parameter BUSER_ENABLE = 0,
parameter BUSER_WIDTH = 1, parameter BUSER_WIDTH = 1,
parameter AW_REG_ENABLE = 1, parameter AW_REG_TYPE = 1,
parameter W_REG_ENABLE = 1, parameter W_REG_TYPE = 2,
parameter B_REG_ENABLE = 1 parameter B_REG_TYPE = 1
) )
( (
input wire clk, input wire clk,
@ -110,7 +110,8 @@ generate
// AW channel // AW channel
if (AW_REG_ENABLE) begin if (AW_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers // datapath registers
reg s_axi_awready_reg = 1'b0; reg s_axi_awready_reg = 1'b0;
@ -245,6 +246,85 @@ always @(posedge clk) begin
end end
end end
end else if (AW_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg s_axi_awready_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}};
reg [7:0] m_axi_awlen_reg = 8'd0;
reg [2:0] m_axi_awsize_reg = 3'd0;
reg [1:0] m_axi_awburst_reg = 2'd0;
reg m_axi_awlock_reg = 1'b0;
reg [3:0] m_axi_awcache_reg = 4'd0;
reg [2:0] m_axi_awprot_reg = 3'd0;
reg [3:0] m_axi_awqos_reg = 4'd0;
reg [3:0] m_axi_awregion_reg = 4'd0;
reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}};
reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
// datapath control
reg store_axi_aw_input_to_output;
assign s_axi_awready = s_axi_awready_reg;
assign m_axi_awid = m_axi_awid_reg;
assign m_axi_awaddr = m_axi_awaddr_reg;
assign m_axi_awlen = m_axi_awlen_reg;
assign m_axi_awsize = m_axi_awsize_reg;
assign m_axi_awburst = m_axi_awburst_reg;
assign m_axi_awlock = m_axi_awlock_reg;
assign m_axi_awcache = m_axi_awcache_reg;
assign m_axi_awprot = m_axi_awprot_reg;
assign m_axi_awqos = m_axi_awqos_reg;
assign m_axi_awregion = m_axi_awregion_reg;
assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
assign m_axi_awvalid = m_axi_awvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axi_awready_eawly = !m_axi_awvalid_next;
always @* begin
// transfer sink ready state to source
m_axi_awvalid_next = m_axi_awvalid_reg;
store_axi_aw_input_to_output = 1'b0;
if (s_axi_awready_reg) begin
m_axi_awvalid_next = s_axi_awvalid;
store_axi_aw_input_to_output = 1'b1;
end else if (m_axi_awready) begin
m_axi_awvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
s_axi_awready_reg <= 1'b0;
m_axi_awvalid_reg <= 1'b0;
end else begin
s_axi_awready_reg <= s_axi_awready_eawly;
m_axi_awvalid_reg <= m_axi_awvalid_next;
end
// datapath
if (store_axi_aw_input_to_output) begin
m_axi_awid_reg <= s_axi_awid;
m_axi_awaddr_reg <= s_axi_awaddr;
m_axi_awlen_reg <= s_axi_awlen;
m_axi_awsize_reg <= s_axi_awsize;
m_axi_awburst_reg <= s_axi_awburst;
m_axi_awlock_reg <= s_axi_awlock;
m_axi_awcache_reg <= s_axi_awcache;
m_axi_awprot_reg <= s_axi_awprot;
m_axi_awqos_reg <= s_axi_awqos;
m_axi_awregion_reg <= s_axi_awregion;
m_axi_awuser_reg <= s_axi_awuser;
end
end
end else begin end else begin
// bypass AW channel // bypass AW channel
@ -266,7 +346,8 @@ end
// W channel // W channel
if (W_REG_ENABLE) begin if (W_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers // datapath registers
reg s_axi_wready_reg = 1'b0; reg s_axi_wready_reg = 1'b0;
@ -359,6 +440,64 @@ always @(posedge clk) begin
end end
end end
end else if (W_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg s_axi_wready_reg = 1'b0;
reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};
reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};
reg m_axi_wlast_reg = 1'b0;
reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};
reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
// datapath control
reg store_axi_w_input_to_output;
assign s_axi_wready = s_axi_wready_reg;
assign m_axi_wdata = m_axi_wdata_reg;
assign m_axi_wstrb = m_axi_wstrb_reg;
assign m_axi_wlast = m_axi_wlast_reg;
assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
assign m_axi_wvalid = m_axi_wvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axi_wready_ewly = !m_axi_wvalid_next;
always @* begin
// transfer sink ready state to source
m_axi_wvalid_next = m_axi_wvalid_reg;
store_axi_w_input_to_output = 1'b0;
if (s_axi_wready_reg) begin
m_axi_wvalid_next = s_axi_wvalid;
store_axi_w_input_to_output = 1'b1;
end else if (m_axi_wready) begin
m_axi_wvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
s_axi_wready_reg <= 1'b0;
m_axi_wvalid_reg <= 1'b0;
end else begin
s_axi_wready_reg <= s_axi_wready_ewly;
m_axi_wvalid_reg <= m_axi_wvalid_next;
end
// datapath
if (store_axi_w_input_to_output) begin
m_axi_wdata_reg <= s_axi_wdata;
m_axi_wstrb_reg <= s_axi_wstrb;
m_axi_wlast_reg <= s_axi_wlast;
m_axi_wuser_reg <= s_axi_wuser;
end
end
end else begin end else begin
// bypass W channel // bypass W channel
@ -373,7 +512,8 @@ end
// B channel // B channel
if (B_REG_ENABLE) begin if (B_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers // datapath registers
reg m_axi_bready_reg = 1'b0; reg m_axi_bready_reg = 1'b0;
@ -460,6 +600,61 @@ always @(posedge clk) begin
end end
end end
end else if (B_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg m_axi_bready_reg = 1'b0;
reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}};
reg [1:0] s_axi_bresp_reg = 2'b0;
reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}};
reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
// datapath control
reg store_axi_b_input_to_output;
assign m_axi_bready = m_axi_bready_reg;
assign s_axi_bid = s_axi_bid_reg;
assign s_axi_bresp = s_axi_bresp_reg;
assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
assign s_axi_bvalid = s_axi_bvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire m_axi_bready_early = !s_axi_bvalid_next;
always @* begin
// transfer sink ready state to source
s_axi_bvalid_next = s_axi_bvalid_reg;
store_axi_b_input_to_output = 1'b0;
if (m_axi_bready_reg) begin
s_axi_bvalid_next = m_axi_bvalid;
store_axi_b_input_to_output = 1'b1;
end else if (s_axi_bready) begin
s_axi_bvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
m_axi_bready_reg <= 1'b0;
s_axi_bvalid_reg <= 1'b0;
end else begin
m_axi_bready_reg <= m_axi_bready_early;
s_axi_bvalid_reg <= s_axi_bvalid_next;
end
// datapath
if (store_axi_b_input_to_output) begin
s_axi_bid_reg <= m_axi_bid;
s_axi_bresp_reg <= m_axi_bresp;
s_axi_buser_reg <= m_axi_buser;
end
end
end else begin end else begin
// bypass B channel // bypass B channel

10
tb/test_axi_register.py
View File

@ -59,11 +59,11 @@ def bench():
ARUSER_WIDTH = 1 ARUSER_WIDTH = 1
RUSER_ENABLE = 0 RUSER_ENABLE = 0
RUSER_WIDTH = 1 RUSER_WIDTH = 1
AW_REG_ENABLE = 1 AW_REG_TYPE = 1
W_REG_ENABLE = 1 W_REG_TYPE = 2
B_REG_ENABLE = 1 B_REG_TYPE = 1
AR_REG_ENABLE = 1 AR_REG_TYPE = 1
R_REG_ENABLE = 1 R_REG_TYPE = 2
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

20
tb/test_axi_register.v
View File

@ -46,11 +46,11 @@ parameter ARUSER_ENABLE = 0;
parameter ARUSER_WIDTH = 1; parameter ARUSER_WIDTH = 1;
parameter RUSER_ENABLE = 0; parameter RUSER_ENABLE = 0;
parameter RUSER_WIDTH = 1; parameter RUSER_WIDTH = 1;
parameter AW_REG_ENABLE = 1; parameter AW_REG_TYPE = 1;
parameter W_REG_ENABLE = 1; parameter W_REG_TYPE = 2;
parameter B_REG_ENABLE = 1; parameter B_REG_TYPE = 1;
parameter AR_REG_ENABLE = 1; parameter AR_REG_TYPE = 1;
parameter R_REG_ENABLE = 1; parameter R_REG_TYPE = 2;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -266,11 +266,11 @@ axi_register #(
.ARUSER_WIDTH(ARUSER_WIDTH), .ARUSER_WIDTH(ARUSER_WIDTH),
.RUSER_ENABLE(RUSER_ENABLE), .RUSER_ENABLE(RUSER_ENABLE),
.RUSER_WIDTH(RUSER_WIDTH), .RUSER_WIDTH(RUSER_WIDTH),
.AW_REG_ENABLE(AW_REG_ENABLE), .AW_REG_TYPE(AW_REG_TYPE),
.W_REG_ENABLE(W_REG_ENABLE), .W_REG_TYPE(W_REG_TYPE),
.B_REG_ENABLE(B_REG_ENABLE), .B_REG_TYPE(B_REG_TYPE),
.AR_REG_ENABLE(AR_REG_ENABLE), .AR_REG_TYPE(AR_REG_TYPE),
.R_REG_ENABLE(R_REG_ENABLE) .R_REG_TYPE(R_REG_TYPE)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

4
tb/test_axi_register_rd.py
View File

@ -51,8 +51,8 @@ def bench():
ARUSER_WIDTH = 1 ARUSER_WIDTH = 1
RUSER_ENABLE = 0 RUSER_ENABLE = 0
RUSER_WIDTH = 1 RUSER_WIDTH = 1
AR_REG_ENABLE = 1 AR_REG_TYPE = 1
R_REG_ENABLE = 1 R_REG_TYPE = 2
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

8
tb/test_axi_register_rd.v
View File

@ -40,8 +40,8 @@ parameter ARUSER_ENABLE = 0;
parameter ARUSER_WIDTH = 1; parameter ARUSER_WIDTH = 1;
parameter RUSER_ENABLE = 0; parameter RUSER_ENABLE = 0;
parameter RUSER_WIDTH = 1; parameter RUSER_WIDTH = 1;
parameter AR_REG_ENABLE = 1; parameter AR_REG_TYPE = 1;
parameter R_REG_ENABLE = 1; parameter R_REG_TYPE = 2;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -155,8 +155,8 @@ axi_register_rd #(
.ARUSER_WIDTH(ARUSER_WIDTH), .ARUSER_WIDTH(ARUSER_WIDTH),
.RUSER_ENABLE(RUSER_ENABLE), .RUSER_ENABLE(RUSER_ENABLE),
.RUSER_WIDTH(RUSER_WIDTH), .RUSER_WIDTH(RUSER_WIDTH),
.AR_REG_ENABLE(AR_REG_ENABLE), .AR_REG_TYPE(AR_REG_TYPE),
.R_REG_ENABLE(R_REG_ENABLE) .R_REG_TYPE(R_REG_TYPE)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

6
tb/test_axi_register_wr.py
View File

@ -53,9 +53,9 @@ def bench():
WUSER_WIDTH = 1 WUSER_WIDTH = 1
BUSER_ENABLE = 0 BUSER_ENABLE = 0
BUSER_WIDTH = 1 BUSER_WIDTH = 1
AW_REG_ENABLE = 1 AW_REG_TYPE = 1
W_REG_ENABLE = 1 W_REG_TYPE = 2
B_REG_ENABLE = 1 B_REG_TYPE = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

12
tb/test_axi_register_wr.v
View File

@ -42,9 +42,9 @@ parameter WUSER_ENABLE = 0;
parameter WUSER_WIDTH = 1; parameter WUSER_WIDTH = 1;
parameter BUSER_ENABLE = 0; parameter BUSER_ENABLE = 0;
parameter BUSER_WIDTH = 1; parameter BUSER_WIDTH = 1;
parameter AW_REG_ENABLE = 1; parameter AW_REG_TYPE = 1;
parameter W_REG_ENABLE = 1; parameter W_REG_TYPE = 2;
parameter B_REG_ENABLE = 1; parameter B_REG_TYPE = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -176,9 +176,9 @@ axi_register_wr #(
.WUSER_WIDTH(WUSER_WIDTH), .WUSER_WIDTH(WUSER_WIDTH),
.BUSER_ENABLE(BUSER_ENABLE), .BUSER_ENABLE(BUSER_ENABLE),
.BUSER_WIDTH(BUSER_WIDTH), .BUSER_WIDTH(BUSER_WIDTH),
.AW_REG_ENABLE(AW_REG_ENABLE), .AW_REG_TYPE(AW_REG_TYPE),
.W_REG_ENABLE(W_REG_ENABLE), .W_REG_TYPE(W_REG_TYPE),
.B_REG_ENABLE(B_REG_ENABLE) .B_REG_TYPE(B_REG_TYPE)
) )
UUT ( UUT (
.clk(clk), .clk(clk),