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https://github.com/alexforencich/verilog-axi.git
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Add zero offset reg
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@ -192,6 +192,7 @@ reg [LEN_WIDTH-1:0] op_word_count_reg = {LEN_WIDTH{1'b0}}, op_word_count_next;
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reg [LEN_WIDTH-1:0] tr_word_count_reg = {LEN_WIDTH{1'b0}}, tr_word_count_next;
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reg [OFFSET_WIDTH-1:0] offset_reg = {OFFSET_WIDTH{1'b0}}, offset_next;
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reg zero_offset_reg = 1'b1, zero_offset_next;
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reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
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reg [LEN_WIDTH-1:0] length_reg = {LEN_WIDTH{1'b0}}, length_next;
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reg [CYCLE_COUNT_WIDTH-1:0] input_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, input_cycle_count_next;
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@ -283,7 +284,7 @@ wire [AXI_ADDR_WIDTH-1:0] addr_plus_max_burst = addr_reg + AXI_MAX_BURST_SIZE;
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wire [AXI_ADDR_WIDTH-1:0] addr_plus_count = addr_reg + op_word_count_reg;
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always @* begin
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if (!ENABLE_UNALIGNED || offset_reg == 0) begin
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if (!ENABLE_UNALIGNED || zero_offset_reg) begin
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// passthrough if no overlap
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shift_axis_tdata = s_axis_write_data_tdata;
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shift_axis_tkeep = s_axis_write_data_tkeep;
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@ -342,6 +343,7 @@ always @* begin
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addr_next = addr_reg;
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offset_next = offset_reg;
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zero_offset_next = zero_offset_reg;
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last_cycle_offset_next = last_cycle_offset_reg;
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length_next = length_reg;
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op_word_count_next = op_word_count_reg;
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@ -377,10 +379,12 @@ always @* begin
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if (ENABLE_UNALIGNED) begin
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addr_next = s_axis_write_desc_addr;
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offset_next = s_axis_write_desc_addr & OFFSET_MASK;
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zero_offset_next = (s_axis_write_desc_addr & OFFSET_MASK) == 0;
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last_cycle_offset_next = offset_next + (s_axis_write_desc_len & OFFSET_MASK);
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end else begin
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addr_next = s_axis_write_desc_addr & ADDR_MASK;
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offset_next = 0;
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zero_offset_next = 1'b1;
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last_cycle_offset_next = offset_next + (s_axis_write_desc_len & OFFSET_MASK);
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end
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tag_next = s_axis_write_desc_tag;
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@ -753,6 +757,7 @@ always @(posedge clk) begin
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addr_reg <= addr_next;
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offset_reg <= offset_next;
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zero_offset_reg <= zero_offset_next;
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last_cycle_offset_reg <= last_cycle_offset_next;
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length_reg <= length_next;
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op_word_count_reg <= op_word_count_next;
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