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Add AXI lite dual-port RAM module and testbench

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Alex Forencich 2019-01-17 17:48:23 -08:00
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Lite dual port RAM
*/
module axil_dp_ram #
(
parameter DATA_WIDTH = 32, // width of data bus in bits
parameter ADDR_WIDTH = 16, // width of address bus in bits
parameter STRB_WIDTH = (DATA_WIDTH/8),
parameter PIPELINE_OUTPUT = 0
)
(
input wire a_clk,
input wire a_rst,
input wire b_clk,
input wire b_rst,
input wire [ADDR_WIDTH-1:0] s_axil_a_awaddr,
input wire [2:0] s_axil_a_awprot,
input wire s_axil_a_awvalid,
output wire s_axil_a_awready,
input wire [DATA_WIDTH-1:0] s_axil_a_wdata,
input wire [STRB_WIDTH-1:0] s_axil_a_wstrb,
input wire s_axil_a_wvalid,
output wire s_axil_a_wready,
output wire [1:0] s_axil_a_bresp,
output wire s_axil_a_bvalid,
input wire s_axil_a_bready,
input wire [ADDR_WIDTH-1:0] s_axil_a_araddr,
input wire [2:0] s_axil_a_arprot,
input wire s_axil_a_arvalid,
output wire s_axil_a_arready,
output wire [DATA_WIDTH-1:0] s_axil_a_rdata,
output wire [1:0] s_axil_a_rresp,
output wire s_axil_a_rvalid,
input wire s_axil_a_rready,
input wire [ADDR_WIDTH-1:0] s_axil_b_awaddr,
input wire [2:0] s_axil_b_awprot,
input wire s_axil_b_awvalid,
output wire s_axil_b_awready,
input wire [DATA_WIDTH-1:0] s_axil_b_wdata,
input wire [STRB_WIDTH-1:0] s_axil_b_wstrb,
input wire s_axil_b_wvalid,
output wire s_axil_b_wready,
output wire [1:0] s_axil_b_bresp,
output wire s_axil_b_bvalid,
input wire s_axil_b_bready,
input wire [ADDR_WIDTH-1:0] s_axil_b_araddr,
input wire [2:0] s_axil_b_arprot,
input wire s_axil_b_arvalid,
output wire s_axil_b_arready,
output wire [DATA_WIDTH-1:0] s_axil_b_rdata,
output wire [1:0] s_axil_b_rresp,
output wire s_axil_b_rvalid,
input wire s_axil_b_rready
);
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
parameter WORD_WIDTH = STRB_WIDTH;
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg read_eligible_a;
reg write_eligible_a;
reg read_eligible_b;
reg write_eligible_b;
reg mem_wr_en_a;
reg mem_rd_en_a;
reg mem_wr_en_b;
reg mem_rd_en_b;
reg last_read_a_reg = 1'b0, last_read_a_next;
reg last_read_b_reg = 1'b0, last_read_b_next;
reg s_axil_a_awready_reg = 1'b0, s_axil_a_awready_next;
reg s_axil_a_wready_reg = 1'b0, s_axil_a_wready_next;
reg [1:0] s_axil_a_bresp_reg = 2'b00, s_axil_a_bresp_next;
reg s_axil_a_bvalid_reg = 1'b0, s_axil_a_bvalid_next;
reg s_axil_a_arready_reg = 1'b0, s_axil_a_arready_next;
reg [DATA_WIDTH-1:0] s_axil_a_rdata_reg = {DATA_WIDTH{1'b0}}, s_axil_a_rdata_next;
reg [1:0] s_axil_a_rresp_reg = 2'b00, s_axil_a_rresp_next;
reg s_axil_a_rvalid_reg = 1'b0, s_axil_a_rvalid_next;
reg [DATA_WIDTH-1:0] s_axil_a_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
reg [1:0] s_axil_a_rresp_pipe_reg = 2'b00;
reg s_axil_a_rvalid_pipe_reg = 1'b0;
reg s_axil_b_awready_reg = 1'b0, s_axil_b_awready_next;
reg s_axil_b_wready_reg = 1'b0, s_axil_b_wready_next;
reg [1:0] s_axil_b_bresp_reg = 2'b00, s_axil_b_bresp_next;
reg s_axil_b_bvalid_reg = 1'b0, s_axil_b_bvalid_next;
reg s_axil_b_arready_reg = 1'b0, s_axil_b_arready_next;
reg [DATA_WIDTH-1:0] s_axil_b_rdata_reg = {DATA_WIDTH{1'b0}}, s_axil_b_rdata_next;
reg [1:0] s_axil_b_rresp_reg = 2'b00, s_axil_b_rresp_next;
reg s_axil_b_rvalid_reg = 1'b0, s_axil_b_rvalid_next;
reg [DATA_WIDTH-1:0] s_axil_b_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
reg [1:0] s_axil_b_rresp_pipe_reg = 2'b00;
reg s_axil_b_rvalid_pipe_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] s_axil_a_awaddr_valid = s_axil_a_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] s_axil_a_araddr_valid = s_axil_a_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] s_axil_b_awaddr_valid = s_axil_b_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] s_axil_b_araddr_valid = s_axil_b_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign s_axil_a_awready = s_axil_a_awready_reg;
assign s_axil_a_wready = s_axil_a_wready_reg;
assign s_axil_a_bresp = s_axil_a_bresp_reg;
assign s_axil_a_bvalid = s_axil_a_bvalid_reg;
assign s_axil_a_arready = s_axil_a_arready_reg;
assign s_axil_a_rdata = PIPELINE_OUTPUT ? s_axil_a_rdata_pipe_reg : s_axil_a_rdata_reg;
assign s_axil_a_rresp = PIPELINE_OUTPUT ? s_axil_a_rresp_pipe_reg : s_axil_a_rresp_reg;
assign s_axil_a_rvalid = PIPELINE_OUTPUT ? s_axil_a_rvalid_pipe_reg : s_axil_a_rvalid_reg;
assign s_axil_b_awready = s_axil_b_awready_reg;
assign s_axil_b_wready = s_axil_b_wready_reg;
assign s_axil_b_bresp = s_axil_b_bresp_reg;
assign s_axil_b_bvalid = s_axil_b_bvalid_reg;
assign s_axil_b_arready = s_axil_b_arready_reg;
assign s_axil_b_rdata = PIPELINE_OUTPUT ? s_axil_b_rdata_pipe_reg : s_axil_b_rdata_reg;
assign s_axil_b_rresp = PIPELINE_OUTPUT ? s_axil_b_rresp_pipe_reg : s_axil_b_rresp_reg;
assign s_axil_b_rvalid = PIPELINE_OUTPUT ? s_axil_b_rvalid_pipe_reg : s_axil_b_rvalid_reg;
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
mem[j] = 0;
end
end
end
always @* begin
mem_wr_en_a = 1'b0;
mem_rd_en_a = 1'b0;
last_read_a_next = last_read_a_reg;
s_axil_a_awready_next = 1'b0;
s_axil_a_wready_next = 1'b0;
s_axil_a_bresp_next = 2'b00;
s_axil_a_bvalid_next = s_axil_a_bvalid_reg && !s_axil_a_bready;
s_axil_a_arready_next = 1'b0;
s_axil_a_rresp_next = 2'b00;
s_axil_a_rvalid_next = s_axil_a_rvalid_reg && !(s_axil_a_rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg));
write_eligible_a = s_axil_a_awvalid && s_axil_a_wvalid && (!s_axil_a_bvalid || s_axil_a_bready) && (!s_axil_a_awready && !s_axil_a_wready);
read_eligible_a = s_axil_a_arvalid && (!s_axil_a_rvalid || s_axil_a_rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg)) && (!s_axil_a_arready);
if (write_eligible_a && (!read_eligible_a || last_read_a_reg)) begin
last_read_a_next = 1'b0;
s_axil_a_awready_next = 1'b1;
s_axil_a_wready_next = 1'b1;
s_axil_a_bresp_next = 2'b00;
s_axil_a_bvalid_next = 1'b1;
mem_wr_en_a = 1'b1;
end else if (read_eligible_a) begin
last_read_a_next = 1'b1;
s_axil_a_arready_next = 1'b1;
s_axil_a_rresp_next = 2'b00;
s_axil_a_rvalid_next = 1'b1;
mem_rd_en_a = 1'b1;
end
end
always @(posedge a_clk) begin
if (a_rst) begin
last_read_a_reg <= 1'b0;
s_axil_a_awready_reg <= 1'b0;
s_axil_a_wready_reg <= 1'b0;
s_axil_a_bvalid_reg <= 1'b0;
s_axil_a_arready_reg <= 1'b0;
s_axil_a_rresp_reg <= 2'b00;
s_axil_a_rvalid_reg <= 1'b0;
s_axil_a_rvalid_pipe_reg <= 1'b0;
end else begin
last_read_a_reg <= last_read_a_next;
s_axil_a_awready_reg <= s_axil_a_awready_next;
s_axil_a_wready_reg <= s_axil_a_wready_next;
s_axil_a_bvalid_reg <= s_axil_a_bvalid_next;
s_axil_a_arready_reg <= s_axil_a_arready_next;
s_axil_a_rresp_reg <= s_axil_a_rresp_next;
s_axil_a_rvalid_reg <= s_axil_a_rvalid_next;
if (!s_axil_a_rvalid_pipe_reg || s_axil_a_rready) begin
s_axil_a_rvalid_pipe_reg <= s_axil_a_rvalid_reg;
end
end
s_axil_a_bresp_reg <= s_axil_a_bresp_next;
if (mem_rd_en_a) begin
s_axil_a_rdata_reg <= mem[s_axil_a_araddr_valid];
end else begin
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (mem_wr_en_a && s_axil_a_wstrb[i]) begin
mem[s_axil_a_awaddr_valid][8*i +: 8] <= s_axil_a_wdata[8*i +: 8];
end
end
end
if (!s_axil_a_rvalid_pipe_reg || s_axil_a_rready) begin
s_axil_a_rdata_pipe_reg <= s_axil_a_rdata_reg;
s_axil_a_rresp_pipe_reg <= s_axil_a_rresp_reg;
end
end
always @* begin
mem_wr_en_b = 1'b0;
mem_rd_en_b = 1'b0;
last_read_b_next = last_read_b_reg;
s_axil_b_awready_next = 1'b0;
s_axil_b_wready_next = 1'b0;
s_axil_b_bresp_next = 2'b00;
s_axil_b_bvalid_next = s_axil_b_bvalid_reg && !s_axil_b_bready;
s_axil_b_arready_next = 1'b0;
s_axil_b_rresp_next = 2'b00;
s_axil_b_rvalid_next = s_axil_b_rvalid_reg && !(s_axil_b_rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg));
write_eligible_b = s_axil_b_awvalid && s_axil_b_wvalid && (!s_axil_b_bvalid || s_axil_b_bready) && (!s_axil_b_awready && !s_axil_b_wready);
read_eligible_b = s_axil_b_arvalid && (!s_axil_b_rvalid || s_axil_b_rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg)) && (!s_axil_b_arready);
if (write_eligible_b && (!read_eligible_b || last_read_b_reg)) begin
last_read_b_next = 1'b0;
s_axil_b_awready_next = 1'b1;
s_axil_b_wready_next = 1'b1;
s_axil_b_bresp_next = 2'b00;
s_axil_b_bvalid_next = 1'b1;
mem_wr_en_b = 1'b1;
end else if (read_eligible_b) begin
last_read_b_next = 1'b1;
s_axil_b_arready_next = 1'b1;
s_axil_b_rresp_next = 2'b00;
s_axil_b_rvalid_next = 1'b1;
mem_rd_en_b = 1'b1;
end
end
always @(posedge a_clk) begin
if (a_rst) begin
last_read_b_reg <= 1'b0;
s_axil_b_awready_reg <= 1'b0;
s_axil_b_wready_reg <= 1'b0;
s_axil_b_bvalid_reg <= 1'b0;
s_axil_b_arready_reg <= 1'b0;
s_axil_b_rresp_reg <= 2'b00;
s_axil_b_rvalid_reg <= 1'b0;
s_axil_b_rvalid_pipe_reg <= 1'b0;
end else begin
last_read_b_reg <= last_read_b_next;
s_axil_b_awready_reg <= s_axil_b_awready_next;
s_axil_b_wready_reg <= s_axil_b_wready_next;
s_axil_b_bvalid_reg <= s_axil_b_bvalid_next;
s_axil_b_arready_reg <= s_axil_b_arready_next;
s_axil_b_rresp_reg <= s_axil_b_rresp_next;
s_axil_b_rvalid_reg <= s_axil_b_rvalid_next;
if (!s_axil_b_rvalid_pipe_reg || s_axil_b_rready) begin
s_axil_b_rvalid_pipe_reg <= s_axil_b_rvalid_reg;
end
end
s_axil_b_bresp_reg <= s_axil_b_bresp_next;
if (mem_rd_en_b) begin
s_axil_b_rdata_reg <= mem[s_axil_b_araddr_valid];
end else begin
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (mem_wr_en_b && s_axil_b_wstrb[i]) begin
mem[s_axil_b_awaddr_valid][8*i +: 8] <= s_axil_b_wdata[8*i +: 8];
end
end
end
if (!s_axil_b_rvalid_pipe_reg || s_axil_b_rready) begin
s_axil_b_rdata_pipe_reg <= s_axil_b_rdata_reg;
s_axil_b_rresp_pipe_reg <= s_axil_b_rresp_reg;
end
end
endmodule

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#!/usr/bin/env python
"""
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
import axil
module = 'axil_dp_ram'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 16
STRB_WIDTH = int(DATA_WIDTH/8)
PIPELINE_OUTPUT = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
a_clk = Signal(bool(0))
a_rst = Signal(bool(0))
b_clk = Signal(bool(0))
b_rst = Signal(bool(0))
s_axil_a_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axil_a_awprot = Signal(intbv(0)[3:])
s_axil_a_awvalid = Signal(bool(0))
s_axil_a_wdata = Signal(intbv(0)[DATA_WIDTH:])
s_axil_a_wstrb = Signal(intbv(0)[STRB_WIDTH:])
s_axil_a_wvalid = Signal(bool(0))
s_axil_a_bready = Signal(bool(0))
s_axil_a_araddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axil_a_arprot = Signal(intbv(0)[3:])
s_axil_a_arvalid = Signal(bool(0))
s_axil_a_rready = Signal(bool(0))
s_axil_b_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axil_b_awprot = Signal(intbv(0)[3:])
s_axil_b_awvalid = Signal(bool(0))
s_axil_b_wdata = Signal(intbv(0)[DATA_WIDTH:])
s_axil_b_wstrb = Signal(intbv(0)[STRB_WIDTH:])
s_axil_b_wvalid = Signal(bool(0))
s_axil_b_bready = Signal(bool(0))
s_axil_b_araddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axil_b_arprot = Signal(intbv(0)[3:])
s_axil_b_arvalid = Signal(bool(0))
s_axil_b_rready = Signal(bool(0))
# Outputs
s_axil_a_awready = Signal(bool(0))
s_axil_a_wready = Signal(bool(0))
s_axil_a_bresp = Signal(intbv(0)[2:])
s_axil_a_bvalid = Signal(bool(0))
s_axil_a_arready = Signal(bool(0))
s_axil_a_rdata = Signal(intbv(0)[DATA_WIDTH:])
s_axil_a_rresp = Signal(intbv(0)[2:])
s_axil_a_rvalid = Signal(bool(0))
s_axil_b_awready = Signal(bool(0))
s_axil_b_wready = Signal(bool(0))
s_axil_b_bresp = Signal(intbv(0)[2:])
s_axil_b_bvalid = Signal(bool(0))
s_axil_b_arready = Signal(bool(0))
s_axil_b_rdata = Signal(intbv(0)[DATA_WIDTH:])
s_axil_b_rresp = Signal(intbv(0)[2:])
s_axil_b_rvalid = Signal(bool(0))
# AXI4-Lite master
axil_a_master_inst = axil.AXILiteMaster()
axil_a_master_pause = Signal(bool(False))
axil_a_master_logic = axil_a_master_inst.create_logic(
a_clk,
a_rst,
m_axil_awaddr=s_axil_a_awaddr,
m_axil_awprot=s_axil_a_awprot,
m_axil_awvalid=s_axil_a_awvalid,
m_axil_awready=s_axil_a_awready,
m_axil_wdata=s_axil_a_wdata,
m_axil_wstrb=s_axil_a_wstrb,
m_axil_wvalid=s_axil_a_wvalid,
m_axil_wready=s_axil_a_wready,
m_axil_bresp=s_axil_a_bresp,
m_axil_bvalid=s_axil_a_bvalid,
m_axil_bready=s_axil_a_bready,
m_axil_araddr=s_axil_a_araddr,
m_axil_arprot=s_axil_a_arprot,
m_axil_arvalid=s_axil_a_arvalid,
m_axil_arready=s_axil_a_arready,
m_axil_rdata=s_axil_a_rdata,
m_axil_rresp=s_axil_a_rresp,
m_axil_rvalid=s_axil_a_rvalid,
m_axil_rready=s_axil_a_rready,
pause=axil_a_master_pause,
name='master_a'
)
axil_b_master_inst = axil.AXILiteMaster()
axil_b_master_pause = Signal(bool(False))
axil_b_master_logic = axil_b_master_inst.create_logic(
b_clk,
b_rst,
m_axil_awaddr=s_axil_b_awaddr,
m_axil_awprot=s_axil_b_awprot,
m_axil_awvalid=s_axil_b_awvalid,
m_axil_awready=s_axil_b_awready,
m_axil_wdata=s_axil_b_wdata,
m_axil_wstrb=s_axil_b_wstrb,
m_axil_wvalid=s_axil_b_wvalid,
m_axil_wready=s_axil_b_wready,
m_axil_bresp=s_axil_b_bresp,
m_axil_bvalid=s_axil_b_bvalid,
m_axil_bready=s_axil_b_bready,
m_axil_araddr=s_axil_b_araddr,
m_axil_arprot=s_axil_b_arprot,
m_axil_arvalid=s_axil_b_arvalid,
m_axil_arready=s_axil_b_arready,
m_axil_rdata=s_axil_b_rdata,
m_axil_rresp=s_axil_b_rresp,
m_axil_rvalid=s_axil_b_rvalid,
m_axil_rready=s_axil_b_rready,
pause=axil_b_master_pause,
name='master_b'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
a_clk=a_clk,
a_rst=a_rst,
b_clk=b_clk,
b_rst=b_rst,
s_axil_a_awaddr=s_axil_a_awaddr,
s_axil_a_awprot=s_axil_a_awprot,
s_axil_a_awvalid=s_axil_a_awvalid,
s_axil_a_awready=s_axil_a_awready,
s_axil_a_wdata=s_axil_a_wdata,
s_axil_a_wstrb=s_axil_a_wstrb,
s_axil_a_wvalid=s_axil_a_wvalid,
s_axil_a_wready=s_axil_a_wready,
s_axil_a_bresp=s_axil_a_bresp,
s_axil_a_bvalid=s_axil_a_bvalid,
s_axil_a_bready=s_axil_a_bready,
s_axil_a_araddr=s_axil_a_araddr,
s_axil_a_arprot=s_axil_a_arprot,
s_axil_a_arvalid=s_axil_a_arvalid,
s_axil_a_arready=s_axil_a_arready,
s_axil_a_rdata=s_axil_a_rdata,
s_axil_a_rresp=s_axil_a_rresp,
s_axil_a_rvalid=s_axil_a_rvalid,
s_axil_a_rready=s_axil_a_rready,
s_axil_b_awaddr=s_axil_b_awaddr,
s_axil_b_awprot=s_axil_b_awprot,
s_axil_b_awvalid=s_axil_b_awvalid,
s_axil_b_awready=s_axil_b_awready,
s_axil_b_wdata=s_axil_b_wdata,
s_axil_b_wstrb=s_axil_b_wstrb,
s_axil_b_wvalid=s_axil_b_wvalid,
s_axil_b_wready=s_axil_b_wready,
s_axil_b_bresp=s_axil_b_bresp,
s_axil_b_bvalid=s_axil_b_bvalid,
s_axil_b_bready=s_axil_b_bready,
s_axil_b_araddr=s_axil_b_araddr,
s_axil_b_arprot=s_axil_b_arprot,
s_axil_b_arvalid=s_axil_b_arvalid,
s_axil_b_arready=s_axil_b_arready,
s_axil_b_rdata=s_axil_b_rdata,
s_axil_b_rresp=s_axil_b_rresp,
s_axil_b_rvalid=s_axil_b_rvalid,
s_axil_b_rready=s_axil_b_rready
)
@always(delay(4))
def clkgen():
clk.next = not clk
a_clk.next = not a_clk
b_clk.next = not b_clk
def wait_normal():
while not axil_a_master_inst.idle() or not axil_b_master_inst.idle():
yield clk.posedge
def wait_pause_master():
while not axil_a_master_inst.idle() or not axil_b_master_inst.idle():
axil_a_master_pause.next = True
axil_b_master_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axil_a_master_pause.next = False
axil_b_master_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
a_rst.next = 1
b_rst.next = 1
yield clk.posedge
rst.next = 0
a_rst.next = 0
b_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: read and write, port A")
current_test.next = 1
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_a_master_inst.init_write(addr, test_data)
yield axil_a_master_inst.wait()
yield clk.posedge
axil_a_master_inst.init_read(addr, len(test_data))
yield axil_a_master_inst.wait()
yield clk.posedge
data = axil_a_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 2: read and write, port B")
current_test.next = 2
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_b_master_inst.init_write(addr, test_data)
yield axil_b_master_inst.wait()
yield clk.posedge
axil_b_master_inst.init_read(addr, len(test_data))
yield axil_b_master_inst.wait()
yield clk.posedge
data = axil_b_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 3: various reads and writes on port A")
current_test.next = 3
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_a_master_inst.init_write(addr-4, b'\xAA'*(length+8))
yield axil_a_master_inst.wait()
axil_a_master_inst.init_write(addr, test_data)
yield wait()
axil_a_master_inst.init_read(addr-1, length+2)
yield axil_a_master_inst.wait()
data = axil_a_master_inst.get_read_data()
assert data[0] == addr-1
assert data[1] == b'\xAA'+test_data+b'\xAA'
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_a_master_inst.init_write(addr, test_data)
yield axil_a_master_inst.wait()
axil_a_master_inst.init_read(addr, length)
yield wait()
yield clk.posedge
data = axil_a_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 4: various reads and writes on port B")
current_test.next = 4
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_b_master_inst.init_write(addr-4, b'\xAA'*(length+8))
yield axil_b_master_inst.wait()
axil_b_master_inst.init_write(addr, test_data)
yield wait()
axil_b_master_inst.init_read(addr-1, length+2)
yield axil_b_master_inst.wait()
data = axil_b_master_inst.get_read_data()
assert data[0] == addr-1
assert data[1] == b'\xAA'+test_data+b'\xAA'
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_b_master_inst.init_write(addr, test_data)
yield axil_b_master_inst.wait()
axil_b_master_inst.init_read(addr, length)
yield wait()
yield clk.posedge
data = axil_b_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 5: arbitration test")
current_test.next = 5
for k in range(10):
axil_a_master_inst.init_write(k*256, b'\x11\x22\x33\x44')
axil_a_master_inst.init_read(k*256, 4)
axil_b_master_inst.init_write(k*256, b'\x11\x22\x33\x44')
axil_b_master_inst.init_read(k*256, 4)
yield wait()
for k in range(10):
axil_a_master_inst.get_read_data()
axil_b_master_inst.get_read_data()
yield delay(100)
raise StopSimulation
return instances()
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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tb/test_axil_dp_ram.v Normal file
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@ -0,0 +1,198 @@
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axil_dp_ram
*/
module test_axil_dp_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter STRB_WIDTH = DATA_WIDTH/8;
parameter PIPELINE_OUTPUT = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg a_clk = 0;
reg a_rst = 0;
reg b_clk = 0;
reg b_rst = 0;
reg [ADDR_WIDTH-1:0] s_axil_a_awaddr = 0;
reg [2:0] s_axil_a_awprot = 0;
reg s_axil_a_awvalid = 0;
reg [DATA_WIDTH-1:0] s_axil_a_wdata = 0;
reg [STRB_WIDTH-1:0] s_axil_a_wstrb = 0;
reg s_axil_a_wvalid = 0;
reg s_axil_a_bready = 0;
reg [ADDR_WIDTH-1:0] s_axil_a_araddr = 0;
reg [2:0] s_axil_a_arprot = 0;
reg s_axil_a_arvalid = 0;
reg s_axil_a_rready = 0;
reg [ADDR_WIDTH-1:0] s_axil_b_awaddr = 0;
reg [2:0] s_axil_b_awprot = 0;
reg s_axil_b_awvalid = 0;
reg [DATA_WIDTH-1:0] s_axil_b_wdata = 0;
reg [STRB_WIDTH-1:0] s_axil_b_wstrb = 0;
reg s_axil_b_wvalid = 0;
reg s_axil_b_bready = 0;
reg [ADDR_WIDTH-1:0] s_axil_b_araddr = 0;
reg [2:0] s_axil_b_arprot = 0;
reg s_axil_b_arvalid = 0;
reg s_axil_b_rready = 0;
// Outputs
wire s_axil_a_awready;
wire s_axil_a_wready;
wire [1:0] s_axil_a_bresp;
wire s_axil_a_bvalid;
wire s_axil_a_arready;
wire [DATA_WIDTH-1:0] s_axil_a_rdata;
wire [1:0] s_axil_a_rresp;
wire s_axil_a_rvalid;
wire s_axil_b_awready;
wire s_axil_b_wready;
wire [1:0] s_axil_b_bresp;
wire s_axil_b_bvalid;
wire s_axil_b_arready;
wire [DATA_WIDTH-1:0] s_axil_b_rdata;
wire [1:0] s_axil_b_rresp;
wire s_axil_b_rvalid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
a_clk,
a_rst,
b_clk,
b_rst,
s_axil_a_awaddr,
s_axil_a_awprot,
s_axil_a_awvalid,
s_axil_a_wdata,
s_axil_a_wstrb,
s_axil_a_wvalid,
s_axil_a_bready,
s_axil_a_araddr,
s_axil_a_arprot,
s_axil_a_arvalid,
s_axil_a_rready,
s_axil_b_awaddr,
s_axil_b_awprot,
s_axil_b_awvalid,
s_axil_b_wdata,
s_axil_b_wstrb,
s_axil_b_wvalid,
s_axil_b_bready,
s_axil_b_araddr,
s_axil_b_arprot,
s_axil_b_arvalid,
s_axil_b_rready
);
$to_myhdl(
s_axil_a_awready,
s_axil_a_wready,
s_axil_a_bresp,
s_axil_a_bvalid,
s_axil_a_arready,
s_axil_a_rdata,
s_axil_a_rresp,
s_axil_a_rvalid,
s_axil_b_awready,
s_axil_b_wready,
s_axil_b_bresp,
s_axil_b_bvalid,
s_axil_b_arready,
s_axil_b_rdata,
s_axil_b_rresp,
s_axil_b_rvalid
);
// dump file
$dumpfile("test_axil_dp_ram.lxt");
$dumpvars(0, test_axil_dp_ram);
end
axil_dp_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
)
UUT (
.a_clk(a_clk),
.a_rst(a_rst),
.b_clk(b_clk),
.b_rst(b_rst),
.s_axil_a_awaddr(s_axil_a_awaddr),
.s_axil_a_awprot(s_axil_a_awprot),
.s_axil_a_awvalid(s_axil_a_awvalid),
.s_axil_a_awready(s_axil_a_awready),
.s_axil_a_wdata(s_axil_a_wdata),
.s_axil_a_wstrb(s_axil_a_wstrb),
.s_axil_a_wvalid(s_axil_a_wvalid),
.s_axil_a_wready(s_axil_a_wready),
.s_axil_a_bresp(s_axil_a_bresp),
.s_axil_a_bvalid(s_axil_a_bvalid),
.s_axil_a_bready(s_axil_a_bready),
.s_axil_a_araddr(s_axil_a_araddr),
.s_axil_a_arprot(s_axil_a_arprot),
.s_axil_a_arvalid(s_axil_a_arvalid),
.s_axil_a_arready(s_axil_a_arready),
.s_axil_a_rdata(s_axil_a_rdata),
.s_axil_a_rresp(s_axil_a_rresp),
.s_axil_a_rvalid(s_axil_a_rvalid),
.s_axil_a_rready(s_axil_a_rready),
.s_axil_b_awaddr(s_axil_b_awaddr),
.s_axil_b_awprot(s_axil_b_awprot),
.s_axil_b_awvalid(s_axil_b_awvalid),
.s_axil_b_awready(s_axil_b_awready),
.s_axil_b_wdata(s_axil_b_wdata),
.s_axil_b_wstrb(s_axil_b_wstrb),
.s_axil_b_wvalid(s_axil_b_wvalid),
.s_axil_b_wready(s_axil_b_wready),
.s_axil_b_bresp(s_axil_b_bresp),
.s_axil_b_bvalid(s_axil_b_bvalid),
.s_axil_b_bready(s_axil_b_bready),
.s_axil_b_araddr(s_axil_b_araddr),
.s_axil_b_arprot(s_axil_b_arprot),
.s_axil_b_arvalid(s_axil_b_arvalid),
.s_axil_b_arready(s_axil_b_arready),
.s_axil_b_rdata(s_axil_b_rdata),
.s_axil_b_rresp(s_axil_b_rresp),
.s_axil_b_rvalid(s_axil_b_rvalid),
.s_axil_b_rready(s_axil_b_rready)
);
endmodule