From 7c40254d7eb89a1596ef885a2fee20e63e302acc Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Tue, 21 Aug 2018 22:27:47 -0700
Subject: [PATCH] Remove redundant testbenches

---
 tb/test_axi_fifo_rd.py       | 305 --------------------------------
 tb/test_axi_fifo_rd.v        | 206 ----------------------
 tb/test_axi_fifo_rd_delay.py | 305 --------------------------------
 tb/test_axi_fifo_rd_delay.v  | 206 ----------------------
 tb/test_axi_fifo_wr.py       | 332 ----------------------------------
 tb/test_axi_fifo_wr.v        | 234 ------------------------
 tb/test_axi_fifo_wr_delay.py | 332 ----------------------------------
 tb/test_axi_fifo_wr_delay.v  | 234 ------------------------
 tb/test_axi_register_rd.py   | 305 --------------------------------
 tb/test_axi_register_rd.v    | 206 ----------------------
 tb/test_axi_register_wr.py   | 333 -----------------------------------
 tb/test_axi_register_wr.v    | 236 -------------------------
 tb/test_axil_register_rd.py  | 233 ------------------------
 tb/test_axil_register_rd.v   | 124 -------------
 tb/test_axil_register_wr.py  | 255 ---------------------------
 tb/test_axil_register_wr.v   | 144 ---------------
 16 files changed, 3990 deletions(-)
 delete mode 100755 tb/test_axi_fifo_rd.py
 delete mode 100644 tb/test_axi_fifo_rd.v
 delete mode 100755 tb/test_axi_fifo_rd_delay.py
 delete mode 100644 tb/test_axi_fifo_rd_delay.v
 delete mode 100755 tb/test_axi_fifo_wr.py
 delete mode 100644 tb/test_axi_fifo_wr.v
 delete mode 100755 tb/test_axi_fifo_wr_delay.py
 delete mode 100644 tb/test_axi_fifo_wr_delay.v
 delete mode 100755 tb/test_axi_register_rd.py
 delete mode 100644 tb/test_axi_register_rd.v
 delete mode 100755 tb/test_axi_register_wr.py
 delete mode 100644 tb/test_axi_register_wr.v
 delete mode 100755 tb/test_axil_register_rd.py
 delete mode 100644 tb/test_axil_register_rd.v
 delete mode 100755 tb/test_axil_register_wr.py
 delete mode 100644 tb/test_axil_register_wr.v

diff --git a/tb/test_axi_fifo_rd.py b/tb/test_axi_fifo_rd.py
deleted file mode 100755
index 64c58bb..0000000
--- a/tb/test_axi_fifo_rd.py
+++ /dev/null
@@ -1,305 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axi
-
-module = 'axi_fifo_rd'
-testbench = 'test_%s' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    ID_WIDTH = 8
-    ARUSER_ENABLE = 0
-    ARUSER_WIDTH = 1
-    RUSER_ENABLE = 0
-    RUSER_WIDTH = 1
-    FIFO_DEPTH = 32
-    FIFO_DELAY = 0
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axi_arid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axi_arlen = Signal(intbv(0)[8:])
-    s_axi_arsize = Signal(intbv(0)[3:])
-    s_axi_arburst = Signal(intbv(0)[2:])
-    s_axi_arlock = Signal(bool(0))
-    s_axi_arcache = Signal(intbv(0)[4:])
-    s_axi_arprot = Signal(intbv(0)[3:])
-    s_axi_arqos = Signal(intbv(0)[4:])
-    s_axi_arregion = Signal(intbv(0)[4:])
-    s_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
-    s_axi_arvalid = Signal(bool(0))
-    s_axi_rready = Signal(bool(0))
-    m_axi_arready = Signal(bool(0))
-    m_axi_rid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axi_rresp = Signal(intbv(0)[2:])
-    m_axi_rlast = Signal(bool(0))
-    m_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
-    m_axi_rvalid = Signal(bool(0))
-
-    # Outputs
-    s_axi_arready = Signal(bool(0))
-    s_axi_rid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axi_rresp = Signal(intbv(0)[2:])
-    s_axi_rlast = Signal(bool(0))
-    s_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
-    s_axi_rvalid = Signal(bool(0))
-    m_axi_arid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axi_arlen = Signal(intbv(0)[8:])
-    m_axi_arsize = Signal(intbv(0)[3:])
-    m_axi_arburst = Signal(intbv(0)[2:])
-    m_axi_arlock = Signal(bool(0))
-    m_axi_arcache = Signal(intbv(0)[4:])
-    m_axi_arprot = Signal(intbv(0)[3:])
-    m_axi_arqos = Signal(intbv(0)[4:])
-    m_axi_arregion = Signal(intbv(0)[4:])
-    m_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
-    m_axi_arvalid = Signal(bool(0))
-    m_axi_rready = Signal(bool(0))
-
-    # AXI4 master
-    axi_master_inst = axi.AXIMaster()
-    axi_master_pause = Signal(bool(False))
-
-    axi_master_logic = axi_master_inst.create_logic(
-        clk,
-        rst,
-        m_axi_arid=s_axi_arid,
-        m_axi_araddr=s_axi_araddr,
-        m_axi_arlen=s_axi_arlen,
-        m_axi_arsize=s_axi_arsize,
-        m_axi_arburst=s_axi_arburst,
-        m_axi_arlock=s_axi_arlock,
-        m_axi_arcache=s_axi_arcache,
-        m_axi_arprot=s_axi_arprot,
-        m_axi_arqos=s_axi_arqos,
-        m_axi_arregion=s_axi_arregion,
-        m_axi_arvalid=s_axi_arvalid,
-        m_axi_arready=s_axi_arready,
-        m_axi_rid=s_axi_rid,
-        m_axi_rdata=s_axi_rdata,
-        m_axi_rresp=s_axi_rresp,
-        m_axi_rlast=s_axi_rlast,
-        m_axi_rvalid=s_axi_rvalid,
-        m_axi_rready=s_axi_rready,
-        pause=axi_master_pause,
-        name='master'
-    )
-
-    # AXI4 RAM model
-    axi_ram_inst = axi.AXIRam(2**16)
-    axi_ram_pause = Signal(bool(False))
-
-    axi_ram_port0 = axi_ram_inst.create_port(
-        clk,
-        s_axi_arid=m_axi_arid,
-        s_axi_araddr=m_axi_araddr,
-        s_axi_arlen=m_axi_arlen,
-        s_axi_arsize=m_axi_arsize,
-        s_axi_arburst=m_axi_arburst,
-        s_axi_arlock=m_axi_arlock,
-        s_axi_arcache=m_axi_arcache,
-        s_axi_arprot=m_axi_arprot,
-        s_axi_arvalid=m_axi_arvalid,
-        s_axi_arready=m_axi_arready,
-        s_axi_rid=m_axi_rid,
-        s_axi_rdata=m_axi_rdata,
-        s_axi_rresp=m_axi_rresp,
-        s_axi_rlast=m_axi_rlast,
-        s_axi_rvalid=m_axi_rvalid,
-        s_axi_rready=m_axi_rready,
-        pause=axi_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axi_arid=s_axi_arid,
-        s_axi_araddr=s_axi_araddr,
-        s_axi_arlen=s_axi_arlen,
-        s_axi_arsize=s_axi_arsize,
-        s_axi_arburst=s_axi_arburst,
-        s_axi_arlock=s_axi_arlock,
-        s_axi_arcache=s_axi_arcache,
-        s_axi_arprot=s_axi_arprot,
-        s_axi_arqos=s_axi_arqos,
-        s_axi_arregion=s_axi_arregion,
-        s_axi_aruser=s_axi_aruser,
-        s_axi_arvalid=s_axi_arvalid,
-        s_axi_arready=s_axi_arready,
-        s_axi_rid=s_axi_rid,
-        s_axi_rdata=s_axi_rdata,
-        s_axi_rresp=s_axi_rresp,
-        s_axi_rlast=s_axi_rlast,
-        s_axi_ruser=s_axi_ruser,
-        s_axi_rvalid=s_axi_rvalid,
-        s_axi_rready=s_axi_rready,
-        m_axi_arid=m_axi_arid,
-        m_axi_araddr=m_axi_araddr,
-        m_axi_arlen=m_axi_arlen,
-        m_axi_arsize=m_axi_arsize,
-        m_axi_arburst=m_axi_arburst,
-        m_axi_arlock=m_axi_arlock,
-        m_axi_arcache=m_axi_arcache,
-        m_axi_arprot=m_axi_arprot,
-        m_axi_arqos=m_axi_arqos,
-        m_axi_arregion=m_axi_arregion,
-        m_axi_aruser=m_axi_aruser,
-        m_axi_arvalid=m_axi_arvalid,
-        m_axi_arready=m_axi_arready,
-        m_axi_rid=m_axi_rid,
-        m_axi_rdata=m_axi_rdata,
-        m_axi_rresp=m_axi_rresp,
-        m_axi_rlast=m_axi_rlast,
-        m_axi_ruser=m_axi_ruser,
-        m_axi_rvalid=m_axi_rvalid,
-        m_axi_rready=m_axi_rready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axi_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axi_master_inst.idle():
-            axi_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axi_master_inst.idle():
-            axi_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: read")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axi_ram_inst.write_mem(addr, test_data)
-
-        axi_master_inst.init_read(addr, len(test_data))
-
-        yield axi_master_inst.wait()
-        yield clk.posedge
-
-        data = axi_master_inst.get_read_data()
-        assert data[0] == addr
-        assert data[1] == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 2: various reads")
-        current_test.next = 2
-
-        for length in list(range(1,8))+[1024]:
-            for offset in list(range(4,8))+[4096-4]:
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    #addr = 256*(16*offset+length)+offset
-                    addr = offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axi_ram_inst.write_mem(addr, test_data)
-
-                    axi_master_inst.init_read(addr, length)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axi_master_inst.get_read_data()
-                    assert data[0] == addr
-                    assert data[1] == test_data
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axi_fifo_rd.v b/tb/test_axi_fifo_rd.v
deleted file mode 100644
index c31a9f8..0000000
--- a/tb/test_axi_fifo_rd.v
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axi_fifo_rd
- */
-module test_axi_fifo_rd;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter ID_WIDTH = 8;
-parameter ARUSER_ENABLE = 0;
-parameter ARUSER_WIDTH = 1;
-parameter RUSER_ENABLE = 0;
-parameter RUSER_WIDTH = 1;
-parameter FIFO_DEPTH = 32;
-parameter FIFO_DELAY = 0;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ID_WIDTH-1:0] s_axi_arid = 0;
-reg [ADDR_WIDTH-1:0] s_axi_araddr = 0;
-reg [7:0] s_axi_arlen = 0;
-reg [2:0] s_axi_arsize = 0;
-reg [1:0] s_axi_arburst = 0;
-reg s_axi_arlock = 0;
-reg [3:0] s_axi_arcache = 0;
-reg [2:0] s_axi_arprot = 0;
-reg [3:0] s_axi_arqos = 0;
-reg [3:0] s_axi_arregion = 0;
-reg [ARUSER_WIDTH-1:0] s_axi_aruser = 0;
-reg s_axi_arvalid = 0;
-reg s_axi_rready = 0;
-reg m_axi_arready = 0;
-reg [ID_WIDTH-1:0] m_axi_rid = 0;
-reg [DATA_WIDTH-1:0] m_axi_rdata = 0;
-reg [1:0] m_axi_rresp = 0;
-reg m_axi_rlast = 0;
-reg [RUSER_WIDTH-1:0] m_axi_ruser = 0;
-reg m_axi_rvalid = 0;
-
-// Outputs
-wire s_axi_arready;
-wire [ID_WIDTH-1:0] s_axi_rid;
-wire [DATA_WIDTH-1:0] s_axi_rdata;
-wire [1:0] s_axi_rresp;
-wire s_axi_rlast;
-wire [RUSER_WIDTH-1:0] s_axi_ruser;
-wire s_axi_rvalid;
-wire [ID_WIDTH-1:0] m_axi_arid;
-wire [ADDR_WIDTH-1:0] m_axi_araddr;
-wire [7:0] m_axi_arlen;
-wire [2:0] m_axi_arsize;
-wire [1:0] m_axi_arburst;
-wire m_axi_arlock;
-wire [3:0] m_axi_arcache;
-wire [2:0] m_axi_arprot;
-wire [3:0] m_axi_arqos;
-wire [3:0] m_axi_arregion;
-wire [ARUSER_WIDTH-1:0] m_axi_aruser;
-wire m_axi_arvalid;
-wire m_axi_rready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axi_arid,
-        s_axi_araddr,
-        s_axi_arlen,
-        s_axi_arsize,
-        s_axi_arburst,
-        s_axi_arlock,
-        s_axi_arcache,
-        s_axi_arprot,
-        s_axi_arqos,
-        s_axi_arregion,
-        s_axi_aruser,
-        s_axi_arvalid,
-        s_axi_rready,
-        m_axi_arready,
-        m_axi_rid,
-        m_axi_rdata,
-        m_axi_rresp,
-        m_axi_rlast,
-        m_axi_ruser,
-        m_axi_rvalid
-    );
-    $to_myhdl(
-        s_axi_arready,
-        s_axi_rid,
-        s_axi_rdata,
-        s_axi_rresp,
-        s_axi_rlast,
-        s_axi_ruser,
-        s_axi_rvalid,
-        m_axi_arid,
-        m_axi_araddr,
-        m_axi_arlen,
-        m_axi_arsize,
-        m_axi_arburst,
-        m_axi_arlock,
-        m_axi_arcache,
-        m_axi_arprot,
-        m_axi_arqos,
-        m_axi_arregion,
-        m_axi_aruser,
-        m_axi_arvalid,
-        m_axi_rready
-    );
-
-    // dump file
-    $dumpfile("test_axi_fifo_rd.lxt");
-    $dumpvars(0, test_axi_fifo_rd);
-end
-
-axi_fifo_rd #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .ID_WIDTH(ID_WIDTH),
-    .ARUSER_ENABLE(ARUSER_ENABLE),
-    .ARUSER_WIDTH(ARUSER_WIDTH),
-    .RUSER_ENABLE(RUSER_ENABLE),
-    .RUSER_WIDTH(RUSER_WIDTH),
-    .FIFO_DEPTH(FIFO_DEPTH),
-    .FIFO_DELAY(FIFO_DELAY)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arqos(s_axi_arqos),
-    .s_axi_arregion(s_axi_arregion),
-    .s_axi_aruser(s_axi_aruser),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(s_axi_ruser),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .m_axi_arid(m_axi_arid),
-    .m_axi_araddr(m_axi_araddr),
-    .m_axi_arlen(m_axi_arlen),
-    .m_axi_arsize(m_axi_arsize),
-    .m_axi_arburst(m_axi_arburst),
-    .m_axi_arlock(m_axi_arlock),
-    .m_axi_arcache(m_axi_arcache),
-    .m_axi_arprot(m_axi_arprot),
-    .m_axi_arqos(m_axi_arqos),
-    .m_axi_arregion(m_axi_arregion),
-    .m_axi_aruser(m_axi_aruser),
-    .m_axi_arvalid(m_axi_arvalid),
-    .m_axi_arready(m_axi_arready),
-    .m_axi_rid(m_axi_rid),
-    .m_axi_rdata(m_axi_rdata),
-    .m_axi_rresp(m_axi_rresp),
-    .m_axi_rlast(m_axi_rlast),
-    .m_axi_ruser(m_axi_ruser),
-    .m_axi_rvalid(m_axi_rvalid),
-    .m_axi_rready(m_axi_rready)
-);
-
-endmodule
diff --git a/tb/test_axi_fifo_rd_delay.py b/tb/test_axi_fifo_rd_delay.py
deleted file mode 100755
index 1bbeb9e..0000000
--- a/tb/test_axi_fifo_rd_delay.py
+++ /dev/null
@@ -1,305 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axi
-
-module = 'axi_fifo_rd'
-testbench = 'test_%s_delay' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    ID_WIDTH = 8
-    ARUSER_ENABLE = 0
-    ARUSER_WIDTH = 1
-    RUSER_ENABLE = 0
-    RUSER_WIDTH = 1
-    FIFO_DEPTH = 32
-    FIFO_DELAY = 1
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axi_arid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axi_arlen = Signal(intbv(0)[8:])
-    s_axi_arsize = Signal(intbv(0)[3:])
-    s_axi_arburst = Signal(intbv(0)[2:])
-    s_axi_arlock = Signal(bool(0))
-    s_axi_arcache = Signal(intbv(0)[4:])
-    s_axi_arprot = Signal(intbv(0)[3:])
-    s_axi_arqos = Signal(intbv(0)[4:])
-    s_axi_arregion = Signal(intbv(0)[4:])
-    s_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
-    s_axi_arvalid = Signal(bool(0))
-    s_axi_rready = Signal(bool(0))
-    m_axi_arready = Signal(bool(0))
-    m_axi_rid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axi_rresp = Signal(intbv(0)[2:])
-    m_axi_rlast = Signal(bool(0))
-    m_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
-    m_axi_rvalid = Signal(bool(0))
-
-    # Outputs
-    s_axi_arready = Signal(bool(0))
-    s_axi_rid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axi_rresp = Signal(intbv(0)[2:])
-    s_axi_rlast = Signal(bool(0))
-    s_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
-    s_axi_rvalid = Signal(bool(0))
-    m_axi_arid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axi_arlen = Signal(intbv(0)[8:])
-    m_axi_arsize = Signal(intbv(0)[3:])
-    m_axi_arburst = Signal(intbv(0)[2:])
-    m_axi_arlock = Signal(bool(0))
-    m_axi_arcache = Signal(intbv(0)[4:])
-    m_axi_arprot = Signal(intbv(0)[3:])
-    m_axi_arqos = Signal(intbv(0)[4:])
-    m_axi_arregion = Signal(intbv(0)[4:])
-    m_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
-    m_axi_arvalid = Signal(bool(0))
-    m_axi_rready = Signal(bool(0))
-
-    # AXI4 master
-    axi_master_inst = axi.AXIMaster()
-    axi_master_pause = Signal(bool(False))
-
-    axi_master_logic = axi_master_inst.create_logic(
-        clk,
-        rst,
-        m_axi_arid=s_axi_arid,
-        m_axi_araddr=s_axi_araddr,
-        m_axi_arlen=s_axi_arlen,
-        m_axi_arsize=s_axi_arsize,
-        m_axi_arburst=s_axi_arburst,
-        m_axi_arlock=s_axi_arlock,
-        m_axi_arcache=s_axi_arcache,
-        m_axi_arprot=s_axi_arprot,
-        m_axi_arqos=s_axi_arqos,
-        m_axi_arregion=s_axi_arregion,
-        m_axi_arvalid=s_axi_arvalid,
-        m_axi_arready=s_axi_arready,
-        m_axi_rid=s_axi_rid,
-        m_axi_rdata=s_axi_rdata,
-        m_axi_rresp=s_axi_rresp,
-        m_axi_rlast=s_axi_rlast,
-        m_axi_rvalid=s_axi_rvalid,
-        m_axi_rready=s_axi_rready,
-        pause=axi_master_pause,
-        name='master'
-    )
-
-    # AXI4 RAM model
-    axi_ram_inst = axi.AXIRam(2**16)
-    axi_ram_pause = Signal(bool(False))
-
-    axi_ram_port0 = axi_ram_inst.create_port(
-        clk,
-        s_axi_arid=m_axi_arid,
-        s_axi_araddr=m_axi_araddr,
-        s_axi_arlen=m_axi_arlen,
-        s_axi_arsize=m_axi_arsize,
-        s_axi_arburst=m_axi_arburst,
-        s_axi_arlock=m_axi_arlock,
-        s_axi_arcache=m_axi_arcache,
-        s_axi_arprot=m_axi_arprot,
-        s_axi_arvalid=m_axi_arvalid,
-        s_axi_arready=m_axi_arready,
-        s_axi_rid=m_axi_rid,
-        s_axi_rdata=m_axi_rdata,
-        s_axi_rresp=m_axi_rresp,
-        s_axi_rlast=m_axi_rlast,
-        s_axi_rvalid=m_axi_rvalid,
-        s_axi_rready=m_axi_rready,
-        pause=axi_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axi_arid=s_axi_arid,
-        s_axi_araddr=s_axi_araddr,
-        s_axi_arlen=s_axi_arlen,
-        s_axi_arsize=s_axi_arsize,
-        s_axi_arburst=s_axi_arburst,
-        s_axi_arlock=s_axi_arlock,
-        s_axi_arcache=s_axi_arcache,
-        s_axi_arprot=s_axi_arprot,
-        s_axi_arqos=s_axi_arqos,
-        s_axi_arregion=s_axi_arregion,
-        s_axi_aruser=s_axi_aruser,
-        s_axi_arvalid=s_axi_arvalid,
-        s_axi_arready=s_axi_arready,
-        s_axi_rid=s_axi_rid,
-        s_axi_rdata=s_axi_rdata,
-        s_axi_rresp=s_axi_rresp,
-        s_axi_rlast=s_axi_rlast,
-        s_axi_ruser=s_axi_ruser,
-        s_axi_rvalid=s_axi_rvalid,
-        s_axi_rready=s_axi_rready,
-        m_axi_arid=m_axi_arid,
-        m_axi_araddr=m_axi_araddr,
-        m_axi_arlen=m_axi_arlen,
-        m_axi_arsize=m_axi_arsize,
-        m_axi_arburst=m_axi_arburst,
-        m_axi_arlock=m_axi_arlock,
-        m_axi_arcache=m_axi_arcache,
-        m_axi_arprot=m_axi_arprot,
-        m_axi_arqos=m_axi_arqos,
-        m_axi_arregion=m_axi_arregion,
-        m_axi_aruser=m_axi_aruser,
-        m_axi_arvalid=m_axi_arvalid,
-        m_axi_arready=m_axi_arready,
-        m_axi_rid=m_axi_rid,
-        m_axi_rdata=m_axi_rdata,
-        m_axi_rresp=m_axi_rresp,
-        m_axi_rlast=m_axi_rlast,
-        m_axi_ruser=m_axi_ruser,
-        m_axi_rvalid=m_axi_rvalid,
-        m_axi_rready=m_axi_rready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axi_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axi_master_inst.idle():
-            axi_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axi_master_inst.idle():
-            axi_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: read")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axi_ram_inst.write_mem(addr, test_data)
-
-        axi_master_inst.init_read(addr, len(test_data))
-
-        yield axi_master_inst.wait()
-        yield clk.posedge
-
-        data = axi_master_inst.get_read_data()
-        assert data[0] == addr
-        assert data[1] == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 2: various reads")
-        current_test.next = 2
-
-        for length in list(range(1,8))+[1024]:
-            for offset in list(range(4,8))+[4096-4]:
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    #addr = 256*(16*offset+length)+offset
-                    addr = offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axi_ram_inst.write_mem(addr, test_data)
-
-                    axi_master_inst.init_read(addr, length)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axi_master_inst.get_read_data()
-                    assert data[0] == addr
-                    assert data[1] == test_data
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axi_fifo_rd_delay.v b/tb/test_axi_fifo_rd_delay.v
deleted file mode 100644
index 18f88ea..0000000
--- a/tb/test_axi_fifo_rd_delay.v
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axi_fifo_rd
- */
-module test_axi_fifo_rd_delay;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter ID_WIDTH = 8;
-parameter ARUSER_ENABLE = 0;
-parameter ARUSER_WIDTH = 1;
-parameter RUSER_ENABLE = 0;
-parameter RUSER_WIDTH = 1;
-parameter FIFO_DEPTH = 32;
-parameter FIFO_DELAY = 1;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ID_WIDTH-1:0] s_axi_arid = 0;
-reg [ADDR_WIDTH-1:0] s_axi_araddr = 0;
-reg [7:0] s_axi_arlen = 0;
-reg [2:0] s_axi_arsize = 0;
-reg [1:0] s_axi_arburst = 0;
-reg s_axi_arlock = 0;
-reg [3:0] s_axi_arcache = 0;
-reg [2:0] s_axi_arprot = 0;
-reg [3:0] s_axi_arqos = 0;
-reg [3:0] s_axi_arregion = 0;
-reg [ARUSER_WIDTH-1:0] s_axi_aruser = 0;
-reg s_axi_arvalid = 0;
-reg s_axi_rready = 0;
-reg m_axi_arready = 0;
-reg [ID_WIDTH-1:0] m_axi_rid = 0;
-reg [DATA_WIDTH-1:0] m_axi_rdata = 0;
-reg [1:0] m_axi_rresp = 0;
-reg m_axi_rlast = 0;
-reg [RUSER_WIDTH-1:0] m_axi_ruser = 0;
-reg m_axi_rvalid = 0;
-
-// Outputs
-wire s_axi_arready;
-wire [ID_WIDTH-1:0] s_axi_rid;
-wire [DATA_WIDTH-1:0] s_axi_rdata;
-wire [1:0] s_axi_rresp;
-wire s_axi_rlast;
-wire [RUSER_WIDTH-1:0] s_axi_ruser;
-wire s_axi_rvalid;
-wire [ID_WIDTH-1:0] m_axi_arid;
-wire [ADDR_WIDTH-1:0] m_axi_araddr;
-wire [7:0] m_axi_arlen;
-wire [2:0] m_axi_arsize;
-wire [1:0] m_axi_arburst;
-wire m_axi_arlock;
-wire [3:0] m_axi_arcache;
-wire [2:0] m_axi_arprot;
-wire [3:0] m_axi_arqos;
-wire [3:0] m_axi_arregion;
-wire [ARUSER_WIDTH-1:0] m_axi_aruser;
-wire m_axi_arvalid;
-wire m_axi_rready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axi_arid,
-        s_axi_araddr,
-        s_axi_arlen,
-        s_axi_arsize,
-        s_axi_arburst,
-        s_axi_arlock,
-        s_axi_arcache,
-        s_axi_arprot,
-        s_axi_arqos,
-        s_axi_arregion,
-        s_axi_aruser,
-        s_axi_arvalid,
-        s_axi_rready,
-        m_axi_arready,
-        m_axi_rid,
-        m_axi_rdata,
-        m_axi_rresp,
-        m_axi_rlast,
-        m_axi_ruser,
-        m_axi_rvalid
-    );
-    $to_myhdl(
-        s_axi_arready,
-        s_axi_rid,
-        s_axi_rdata,
-        s_axi_rresp,
-        s_axi_rlast,
-        s_axi_ruser,
-        s_axi_rvalid,
-        m_axi_arid,
-        m_axi_araddr,
-        m_axi_arlen,
-        m_axi_arsize,
-        m_axi_arburst,
-        m_axi_arlock,
-        m_axi_arcache,
-        m_axi_arprot,
-        m_axi_arqos,
-        m_axi_arregion,
-        m_axi_aruser,
-        m_axi_arvalid,
-        m_axi_rready
-    );
-
-    // dump file
-    $dumpfile("test_axi_fifo_rd_delay.lxt");
-    $dumpvars(0, test_axi_fifo_rd_delay);
-end
-
-axi_fifo_rd #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .ID_WIDTH(ID_WIDTH),
-    .ARUSER_ENABLE(ARUSER_ENABLE),
-    .ARUSER_WIDTH(ARUSER_WIDTH),
-    .RUSER_ENABLE(RUSER_ENABLE),
-    .RUSER_WIDTH(RUSER_WIDTH),
-    .FIFO_DEPTH(FIFO_DEPTH),
-    .FIFO_DELAY(FIFO_DELAY)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arqos(s_axi_arqos),
-    .s_axi_arregion(s_axi_arregion),
-    .s_axi_aruser(s_axi_aruser),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(s_axi_ruser),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .m_axi_arid(m_axi_arid),
-    .m_axi_araddr(m_axi_araddr),
-    .m_axi_arlen(m_axi_arlen),
-    .m_axi_arsize(m_axi_arsize),
-    .m_axi_arburst(m_axi_arburst),
-    .m_axi_arlock(m_axi_arlock),
-    .m_axi_arcache(m_axi_arcache),
-    .m_axi_arprot(m_axi_arprot),
-    .m_axi_arqos(m_axi_arqos),
-    .m_axi_arregion(m_axi_arregion),
-    .m_axi_aruser(m_axi_aruser),
-    .m_axi_arvalid(m_axi_arvalid),
-    .m_axi_arready(m_axi_arready),
-    .m_axi_rid(m_axi_rid),
-    .m_axi_rdata(m_axi_rdata),
-    .m_axi_rresp(m_axi_rresp),
-    .m_axi_rlast(m_axi_rlast),
-    .m_axi_ruser(m_axi_ruser),
-    .m_axi_rvalid(m_axi_rvalid),
-    .m_axi_rready(m_axi_rready)
-);
-
-endmodule
diff --git a/tb/test_axi_fifo_wr.py b/tb/test_axi_fifo_wr.py
deleted file mode 100755
index e207e2c..0000000
--- a/tb/test_axi_fifo_wr.py
+++ /dev/null
@@ -1,332 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axi
-
-module = 'axi_fifo_wr'
-testbench = 'test_%s' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    ID_WIDTH = 8
-    AWUSER_ENABLE = 0
-    AWUSER_WIDTH = 1
-    WUSER_ENABLE = 0
-    WUSER_WIDTH = 1
-    BUSER_ENABLE = 0
-    BUSER_WIDTH = 1
-    FIFO_DEPTH = 32
-    FIFO_DELAY = 0
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axi_awid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axi_awlen = Signal(intbv(0)[8:])
-    s_axi_awsize = Signal(intbv(0)[3:])
-    s_axi_awburst = Signal(intbv(0)[2:])
-    s_axi_awlock = Signal(bool(0))
-    s_axi_awcache = Signal(intbv(0)[4:])
-    s_axi_awprot = Signal(intbv(0)[3:])
-    s_axi_awqos = Signal(intbv(0)[4:])
-    s_axi_awregion = Signal(intbv(0)[4:])
-    s_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
-    s_axi_awvalid = Signal(bool(0))
-    s_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    s_axi_wlast = Signal(bool(0))
-    s_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
-    s_axi_wvalid = Signal(bool(0))
-    s_axi_bready = Signal(bool(0))
-    m_axi_awready = Signal(bool(0))
-    m_axi_wready = Signal(bool(0))
-    m_axi_bid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_bresp = Signal(intbv(0)[2:])
-    m_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
-    m_axi_bvalid = Signal(bool(0))
-
-    # Outputs
-    s_axi_awready = Signal(bool(0))
-    s_axi_wready = Signal(bool(0))
-    s_axi_bid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_bresp = Signal(intbv(0)[2:])
-    s_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
-    s_axi_bvalid = Signal(bool(0))
-    m_axi_awid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axi_awlen = Signal(intbv(0)[8:])
-    m_axi_awsize = Signal(intbv(0)[3:])
-    m_axi_awburst = Signal(intbv(0)[2:])
-    m_axi_awlock = Signal(bool(0))
-    m_axi_awcache = Signal(intbv(0)[4:])
-    m_axi_awprot = Signal(intbv(0)[3:])
-    m_axi_awqos = Signal(intbv(0)[4:])
-    m_axi_awregion = Signal(intbv(0)[4:])
-    m_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
-    m_axi_awvalid = Signal(bool(0))
-    m_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    m_axi_wlast = Signal(bool(0))
-    m_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
-    m_axi_wvalid = Signal(bool(0))
-    m_axi_bready = Signal(bool(0))
-
-    # AXI4 master
-    axi_master_inst = axi.AXIMaster()
-    axi_master_pause = Signal(bool(False))
-
-    axi_master_logic = axi_master_inst.create_logic(
-        clk,
-        rst,
-        m_axi_awid=s_axi_awid,
-        m_axi_awaddr=s_axi_awaddr,
-        m_axi_awlen=s_axi_awlen,
-        m_axi_awsize=s_axi_awsize,
-        m_axi_awburst=s_axi_awburst,
-        m_axi_awlock=s_axi_awlock,
-        m_axi_awcache=s_axi_awcache,
-        m_axi_awprot=s_axi_awprot,
-        m_axi_awqos=s_axi_awqos,
-        m_axi_awregion=s_axi_awregion,
-        m_axi_awvalid=s_axi_awvalid,
-        m_axi_awready=s_axi_awready,
-        m_axi_wdata=s_axi_wdata,
-        m_axi_wstrb=s_axi_wstrb,
-        m_axi_wlast=s_axi_wlast,
-        m_axi_wvalid=s_axi_wvalid,
-        m_axi_wready=s_axi_wready,
-        m_axi_bid=s_axi_bid,
-        m_axi_bresp=s_axi_bresp,
-        m_axi_bvalid=s_axi_bvalid,
-        m_axi_bready=s_axi_bready,
-        pause=axi_master_pause,
-        name='master'
-    )
-
-    # AXI4 RAM model
-    axi_ram_inst = axi.AXIRam(2**16)
-    axi_ram_pause = Signal(bool(False))
-
-    axi_ram_port0 = axi_ram_inst.create_port(
-        clk,
-        s_axi_awid=m_axi_awid,
-        s_axi_awaddr=m_axi_awaddr,
-        s_axi_awlen=m_axi_awlen,
-        s_axi_awsize=m_axi_awsize,
-        s_axi_awburst=m_axi_awburst,
-        s_axi_awlock=m_axi_awlock,
-        s_axi_awcache=m_axi_awcache,
-        s_axi_awprot=m_axi_awprot,
-        s_axi_awvalid=m_axi_awvalid,
-        s_axi_awready=m_axi_awready,
-        s_axi_wdata=m_axi_wdata,
-        s_axi_wstrb=m_axi_wstrb,
-        s_axi_wlast=m_axi_wlast,
-        s_axi_wvalid=m_axi_wvalid,
-        s_axi_wready=m_axi_wready,
-        s_axi_bid=m_axi_bid,
-        s_axi_bresp=m_axi_bresp,
-        s_axi_bvalid=m_axi_bvalid,
-        s_axi_bready=m_axi_bready,
-        pause=axi_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axi_awid=s_axi_awid,
-        s_axi_awaddr=s_axi_awaddr,
-        s_axi_awlen=s_axi_awlen,
-        s_axi_awsize=s_axi_awsize,
-        s_axi_awburst=s_axi_awburst,
-        s_axi_awlock=s_axi_awlock,
-        s_axi_awcache=s_axi_awcache,
-        s_axi_awprot=s_axi_awprot,
-        s_axi_awqos=s_axi_awqos,
-        s_axi_awregion=s_axi_awregion,
-        s_axi_awuser=s_axi_awuser,
-        s_axi_awvalid=s_axi_awvalid,
-        s_axi_awready=s_axi_awready,
-        s_axi_wdata=s_axi_wdata,
-        s_axi_wstrb=s_axi_wstrb,
-        s_axi_wlast=s_axi_wlast,
-        s_axi_wuser=s_axi_wuser,
-        s_axi_wvalid=s_axi_wvalid,
-        s_axi_wready=s_axi_wready,
-        s_axi_bid=s_axi_bid,
-        s_axi_bresp=s_axi_bresp,
-        s_axi_buser=s_axi_buser,
-        s_axi_bvalid=s_axi_bvalid,
-        s_axi_bready=s_axi_bready,
-        m_axi_awid=m_axi_awid,
-        m_axi_awaddr=m_axi_awaddr,
-        m_axi_awlen=m_axi_awlen,
-        m_axi_awsize=m_axi_awsize,
-        m_axi_awburst=m_axi_awburst,
-        m_axi_awlock=m_axi_awlock,
-        m_axi_awcache=m_axi_awcache,
-        m_axi_awprot=m_axi_awprot,
-        m_axi_awqos=m_axi_awqos,
-        m_axi_awregion=m_axi_awregion,
-        m_axi_awuser=m_axi_awuser,
-        m_axi_awvalid=m_axi_awvalid,
-        m_axi_awready=m_axi_awready,
-        m_axi_wdata=m_axi_wdata,
-        m_axi_wstrb=m_axi_wstrb,
-        m_axi_wlast=m_axi_wlast,
-        m_axi_wuser=m_axi_wuser,
-        m_axi_wvalid=m_axi_wvalid,
-        m_axi_wready=m_axi_wready,
-        m_axi_bid=m_axi_bid,
-        m_axi_bresp=m_axi_bresp,
-        m_axi_buser=m_axi_buser,
-        m_axi_bvalid=m_axi_bvalid,
-        m_axi_bready=m_axi_bready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axi_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axi_master_inst.idle():
-            axi_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axi_master_inst.idle():
-            axi_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: write")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axi_master_inst.init_write(addr, test_data)
-
-        yield axi_master_inst.wait()
-        yield clk.posedge
-
-        data = axi_ram_inst.read_mem(addr&0xffffff80, 32)
-        for i in range(0, len(data), 16):
-            print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-        assert axi_ram_inst.read_mem(addr, len(test_data)) == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 2: various writes")
-        current_test.next = 2
-
-        for length in list(range(1,8))+[1024]:
-            for offset in list(range(4,8))+[4096-4]:
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    #addr = 256*(16*offset+length)+offset
-                    addr = offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axi_ram_inst.write_mem(addr&0xffffff80, b'\xAA'*(length+256))
-                    axi_master_inst.init_write(addr, test_data)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axi_ram_inst.read_mem(addr&0xffffff80, 32)
-                    for i in range(0, len(data), 16):
-                        print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-                    assert axi_ram_inst.read_mem(addr, length) == test_data
-                    assert axi_ram_inst.read_mem(addr-1, 1) == b'\xAA'
-                    assert axi_ram_inst.read_mem(addr+length, 1) == b'\xAA'
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axi_fifo_wr.v b/tb/test_axi_fifo_wr.v
deleted file mode 100644
index 6cf01fa..0000000
--- a/tb/test_axi_fifo_wr.v
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axi_fifo_wr
- */
-module test_axi_fifo_wr;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter ID_WIDTH = 8;
-parameter AWUSER_ENABLE = 0;
-parameter AWUSER_WIDTH = 1;
-parameter WUSER_ENABLE = 0;
-parameter WUSER_WIDTH = 1;
-parameter BUSER_ENABLE = 0;
-parameter BUSER_WIDTH = 1;
-parameter FIFO_DEPTH = 32;
-parameter FIFO_DELAY = 0;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ID_WIDTH-1:0] s_axi_awid = 0;
-reg [ADDR_WIDTH-1:0] s_axi_awaddr = 0;
-reg [7:0] s_axi_awlen = 0;
-reg [2:0] s_axi_awsize = 0;
-reg [1:0] s_axi_awburst = 0;
-reg s_axi_awlock = 0;
-reg [3:0] s_axi_awcache = 0;
-reg [2:0] s_axi_awprot = 0;
-reg [3:0] s_axi_awqos = 0;
-reg [3:0] s_axi_awregion = 0;
-reg [AWUSER_WIDTH-1:0] s_axi_awuser = 0;
-reg s_axi_awvalid = 0;
-reg [DATA_WIDTH-1:0] s_axi_wdata = 0;
-reg [STRB_WIDTH-1:0] s_axi_wstrb = 0;
-reg s_axi_wlast = 0;
-reg [WUSER_WIDTH-1:0] s_axi_wuser = 0;
-reg s_axi_wvalid = 0;
-reg s_axi_bready = 0;
-reg m_axi_awready = 0;
-reg m_axi_wready = 0;
-reg [ID_WIDTH-1:0] m_axi_bid = 0;
-reg [1:0] m_axi_bresp = 0;
-reg [BUSER_WIDTH-1:0] m_axi_buser = 0;
-reg m_axi_bvalid = 0;
-
-// Outputs
-wire s_axi_awready;
-wire s_axi_wready;
-wire [ID_WIDTH-1:0] s_axi_bid;
-wire [1:0] s_axi_bresp;
-wire [BUSER_WIDTH-1:0] s_axi_buser;
-wire s_axi_bvalid;
-wire [ID_WIDTH-1:0] m_axi_awid;
-wire [ADDR_WIDTH-1:0] m_axi_awaddr;
-wire [7:0] m_axi_awlen;
-wire [2:0] m_axi_awsize;
-wire [1:0] m_axi_awburst;
-wire m_axi_awlock;
-wire [3:0] m_axi_awcache;
-wire [2:0] m_axi_awprot;
-wire [3:0] m_axi_awqos;
-wire [3:0] m_axi_awregion;
-wire [AWUSER_WIDTH-1:0] m_axi_awuser;
-wire m_axi_awvalid;
-wire [DATA_WIDTH-1:0] m_axi_wdata;
-wire [STRB_WIDTH-1:0] m_axi_wstrb;
-wire m_axi_wlast;
-wire [WUSER_WIDTH-1:0] m_axi_wuser;
-wire m_axi_wvalid;
-wire m_axi_bready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axi_awid,
-        s_axi_awaddr,
-        s_axi_awlen,
-        s_axi_awsize,
-        s_axi_awburst,
-        s_axi_awlock,
-        s_axi_awcache,
-        s_axi_awprot,
-        s_axi_awqos,
-        s_axi_awregion,
-        s_axi_awuser,
-        s_axi_awvalid,
-        s_axi_wdata,
-        s_axi_wstrb,
-        s_axi_wlast,
-        s_axi_wuser,
-        s_axi_wvalid,
-        s_axi_bready,
-        m_axi_awready,
-        m_axi_wready,
-        m_axi_bid,
-        m_axi_bresp,
-        m_axi_buser,
-        m_axi_bvalid
-    );
-    $to_myhdl(
-        s_axi_awready,
-        s_axi_wready,
-        s_axi_bid,
-        s_axi_bresp,
-        s_axi_buser,
-        s_axi_bvalid,
-        m_axi_awid,
-        m_axi_awaddr,
-        m_axi_awlen,
-        m_axi_awsize,
-        m_axi_awburst,
-        m_axi_awlock,
-        m_axi_awcache,
-        m_axi_awprot,
-        m_axi_awqos,
-        m_axi_awregion,
-        m_axi_awuser,
-        m_axi_awvalid,
-        m_axi_wdata,
-        m_axi_wstrb,
-        m_axi_wlast,
-        m_axi_wuser,
-        m_axi_wvalid,
-        m_axi_bready
-    );
-
-    // dump file
-    $dumpfile("test_axi_fifo_wr.lxt");
-    $dumpvars(0, test_axi_fifo_wr);
-end
-
-axi_fifo_wr #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .ID_WIDTH(ID_WIDTH),
-    .AWUSER_ENABLE(AWUSER_ENABLE),
-    .AWUSER_WIDTH(AWUSER_WIDTH),
-    .WUSER_ENABLE(WUSER_ENABLE),
-    .WUSER_WIDTH(WUSER_WIDTH),
-    .BUSER_ENABLE(BUSER_ENABLE),
-    .BUSER_WIDTH(BUSER_WIDTH),
-    .FIFO_DEPTH(FIFO_DEPTH),
-    .FIFO_DELAY(FIFO_DELAY)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awregion(s_axi_awregion),
-    .s_axi_awuser(s_axi_awuser),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(s_axi_wuser),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(s_axi_buser),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .m_axi_awid(m_axi_awid),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(m_axi_awlen),
-    .m_axi_awsize(m_axi_awsize),
-    .m_axi_awburst(m_axi_awburst),
-    .m_axi_awlock(m_axi_awlock),
-    .m_axi_awcache(m_axi_awcache),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awqos(m_axi_awqos),
-    .m_axi_awregion(m_axi_awregion),
-    .m_axi_awuser(m_axi_awuser),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(m_axi_wlast),
-    .m_axi_wuser(m_axi_wuser),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(m_axi_bid),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(m_axi_buser),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready)
-);
-
-endmodule
diff --git a/tb/test_axi_fifo_wr_delay.py b/tb/test_axi_fifo_wr_delay.py
deleted file mode 100755
index e924519..0000000
--- a/tb/test_axi_fifo_wr_delay.py
+++ /dev/null
@@ -1,332 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axi
-
-module = 'axi_fifo_wr'
-testbench = 'test_%s_delay' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    ID_WIDTH = 8
-    AWUSER_ENABLE = 0
-    AWUSER_WIDTH = 1
-    WUSER_ENABLE = 0
-    WUSER_WIDTH = 1
-    BUSER_ENABLE = 0
-    BUSER_WIDTH = 1
-    FIFO_DEPTH = 32
-    FIFO_DELAY = 1
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axi_awid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axi_awlen = Signal(intbv(0)[8:])
-    s_axi_awsize = Signal(intbv(0)[3:])
-    s_axi_awburst = Signal(intbv(0)[2:])
-    s_axi_awlock = Signal(bool(0))
-    s_axi_awcache = Signal(intbv(0)[4:])
-    s_axi_awprot = Signal(intbv(0)[3:])
-    s_axi_awqos = Signal(intbv(0)[4:])
-    s_axi_awregion = Signal(intbv(0)[4:])
-    s_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
-    s_axi_awvalid = Signal(bool(0))
-    s_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    s_axi_wlast = Signal(bool(0))
-    s_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
-    s_axi_wvalid = Signal(bool(0))
-    s_axi_bready = Signal(bool(0))
-    m_axi_awready = Signal(bool(0))
-    m_axi_wready = Signal(bool(0))
-    m_axi_bid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_bresp = Signal(intbv(0)[2:])
-    m_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
-    m_axi_bvalid = Signal(bool(0))
-
-    # Outputs
-    s_axi_awready = Signal(bool(0))
-    s_axi_wready = Signal(bool(0))
-    s_axi_bid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_bresp = Signal(intbv(0)[2:])
-    s_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
-    s_axi_bvalid = Signal(bool(0))
-    m_axi_awid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axi_awlen = Signal(intbv(0)[8:])
-    m_axi_awsize = Signal(intbv(0)[3:])
-    m_axi_awburst = Signal(intbv(0)[2:])
-    m_axi_awlock = Signal(bool(0))
-    m_axi_awcache = Signal(intbv(0)[4:])
-    m_axi_awprot = Signal(intbv(0)[3:])
-    m_axi_awqos = Signal(intbv(0)[4:])
-    m_axi_awregion = Signal(intbv(0)[4:])
-    m_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
-    m_axi_awvalid = Signal(bool(0))
-    m_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    m_axi_wlast = Signal(bool(0))
-    m_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
-    m_axi_wvalid = Signal(bool(0))
-    m_axi_bready = Signal(bool(0))
-
-    # AXI4 master
-    axi_master_inst = axi.AXIMaster()
-    axi_master_pause = Signal(bool(False))
-
-    axi_master_logic = axi_master_inst.create_logic(
-        clk,
-        rst,
-        m_axi_awid=s_axi_awid,
-        m_axi_awaddr=s_axi_awaddr,
-        m_axi_awlen=s_axi_awlen,
-        m_axi_awsize=s_axi_awsize,
-        m_axi_awburst=s_axi_awburst,
-        m_axi_awlock=s_axi_awlock,
-        m_axi_awcache=s_axi_awcache,
-        m_axi_awprot=s_axi_awprot,
-        m_axi_awqos=s_axi_awqos,
-        m_axi_awregion=s_axi_awregion,
-        m_axi_awvalid=s_axi_awvalid,
-        m_axi_awready=s_axi_awready,
-        m_axi_wdata=s_axi_wdata,
-        m_axi_wstrb=s_axi_wstrb,
-        m_axi_wlast=s_axi_wlast,
-        m_axi_wvalid=s_axi_wvalid,
-        m_axi_wready=s_axi_wready,
-        m_axi_bid=s_axi_bid,
-        m_axi_bresp=s_axi_bresp,
-        m_axi_bvalid=s_axi_bvalid,
-        m_axi_bready=s_axi_bready,
-        pause=axi_master_pause,
-        name='master'
-    )
-
-    # AXI4 RAM model
-    axi_ram_inst = axi.AXIRam(2**16)
-    axi_ram_pause = Signal(bool(False))
-
-    axi_ram_port0 = axi_ram_inst.create_port(
-        clk,
-        s_axi_awid=m_axi_awid,
-        s_axi_awaddr=m_axi_awaddr,
-        s_axi_awlen=m_axi_awlen,
-        s_axi_awsize=m_axi_awsize,
-        s_axi_awburst=m_axi_awburst,
-        s_axi_awlock=m_axi_awlock,
-        s_axi_awcache=m_axi_awcache,
-        s_axi_awprot=m_axi_awprot,
-        s_axi_awvalid=m_axi_awvalid,
-        s_axi_awready=m_axi_awready,
-        s_axi_wdata=m_axi_wdata,
-        s_axi_wstrb=m_axi_wstrb,
-        s_axi_wlast=m_axi_wlast,
-        s_axi_wvalid=m_axi_wvalid,
-        s_axi_wready=m_axi_wready,
-        s_axi_bid=m_axi_bid,
-        s_axi_bresp=m_axi_bresp,
-        s_axi_bvalid=m_axi_bvalid,
-        s_axi_bready=m_axi_bready,
-        pause=axi_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axi_awid=s_axi_awid,
-        s_axi_awaddr=s_axi_awaddr,
-        s_axi_awlen=s_axi_awlen,
-        s_axi_awsize=s_axi_awsize,
-        s_axi_awburst=s_axi_awburst,
-        s_axi_awlock=s_axi_awlock,
-        s_axi_awcache=s_axi_awcache,
-        s_axi_awprot=s_axi_awprot,
-        s_axi_awqos=s_axi_awqos,
-        s_axi_awregion=s_axi_awregion,
-        s_axi_awuser=s_axi_awuser,
-        s_axi_awvalid=s_axi_awvalid,
-        s_axi_awready=s_axi_awready,
-        s_axi_wdata=s_axi_wdata,
-        s_axi_wstrb=s_axi_wstrb,
-        s_axi_wlast=s_axi_wlast,
-        s_axi_wuser=s_axi_wuser,
-        s_axi_wvalid=s_axi_wvalid,
-        s_axi_wready=s_axi_wready,
-        s_axi_bid=s_axi_bid,
-        s_axi_bresp=s_axi_bresp,
-        s_axi_buser=s_axi_buser,
-        s_axi_bvalid=s_axi_bvalid,
-        s_axi_bready=s_axi_bready,
-        m_axi_awid=m_axi_awid,
-        m_axi_awaddr=m_axi_awaddr,
-        m_axi_awlen=m_axi_awlen,
-        m_axi_awsize=m_axi_awsize,
-        m_axi_awburst=m_axi_awburst,
-        m_axi_awlock=m_axi_awlock,
-        m_axi_awcache=m_axi_awcache,
-        m_axi_awprot=m_axi_awprot,
-        m_axi_awqos=m_axi_awqos,
-        m_axi_awregion=m_axi_awregion,
-        m_axi_awuser=m_axi_awuser,
-        m_axi_awvalid=m_axi_awvalid,
-        m_axi_awready=m_axi_awready,
-        m_axi_wdata=m_axi_wdata,
-        m_axi_wstrb=m_axi_wstrb,
-        m_axi_wlast=m_axi_wlast,
-        m_axi_wuser=m_axi_wuser,
-        m_axi_wvalid=m_axi_wvalid,
-        m_axi_wready=m_axi_wready,
-        m_axi_bid=m_axi_bid,
-        m_axi_bresp=m_axi_bresp,
-        m_axi_buser=m_axi_buser,
-        m_axi_bvalid=m_axi_bvalid,
-        m_axi_bready=m_axi_bready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axi_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axi_master_inst.idle():
-            axi_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axi_master_inst.idle():
-            axi_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: write")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axi_master_inst.init_write(addr, test_data)
-
-        yield axi_master_inst.wait()
-        yield clk.posedge
-
-        data = axi_ram_inst.read_mem(addr&0xffffff80, 32)
-        for i in range(0, len(data), 16):
-            print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-        assert axi_ram_inst.read_mem(addr, len(test_data)) == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 2: various writes")
-        current_test.next = 2
-
-        for length in list(range(1,8))+[1024]:
-            for offset in list(range(4,8))+[4096-4]:
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    #addr = 256*(16*offset+length)+offset
-                    addr = offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axi_ram_inst.write_mem(addr&0xffffff80, b'\xAA'*(length+256))
-                    axi_master_inst.init_write(addr, test_data)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axi_ram_inst.read_mem(addr&0xffffff80, 32)
-                    for i in range(0, len(data), 16):
-                        print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-                    assert axi_ram_inst.read_mem(addr, length) == test_data
-                    assert axi_ram_inst.read_mem(addr-1, 1) == b'\xAA'
-                    assert axi_ram_inst.read_mem(addr+length, 1) == b'\xAA'
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axi_fifo_wr_delay.v b/tb/test_axi_fifo_wr_delay.v
deleted file mode 100644
index 5295e86..0000000
--- a/tb/test_axi_fifo_wr_delay.v
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axi_fifo_wr
- */
-module test_axi_fifo_wr_delay;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter ID_WIDTH = 8;
-parameter AWUSER_ENABLE = 0;
-parameter AWUSER_WIDTH = 1;
-parameter WUSER_ENABLE = 0;
-parameter WUSER_WIDTH = 1;
-parameter BUSER_ENABLE = 0;
-parameter BUSER_WIDTH = 1;
-parameter FIFO_DEPTH = 32;
-parameter FIFO_DELAY = 1;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ID_WIDTH-1:0] s_axi_awid = 0;
-reg [ADDR_WIDTH-1:0] s_axi_awaddr = 0;
-reg [7:0] s_axi_awlen = 0;
-reg [2:0] s_axi_awsize = 0;
-reg [1:0] s_axi_awburst = 0;
-reg s_axi_awlock = 0;
-reg [3:0] s_axi_awcache = 0;
-reg [2:0] s_axi_awprot = 0;
-reg [3:0] s_axi_awqos = 0;
-reg [3:0] s_axi_awregion = 0;
-reg [AWUSER_WIDTH-1:0] s_axi_awuser = 0;
-reg s_axi_awvalid = 0;
-reg [DATA_WIDTH-1:0] s_axi_wdata = 0;
-reg [STRB_WIDTH-1:0] s_axi_wstrb = 0;
-reg s_axi_wlast = 0;
-reg [WUSER_WIDTH-1:0] s_axi_wuser = 0;
-reg s_axi_wvalid = 0;
-reg s_axi_bready = 0;
-reg m_axi_awready = 0;
-reg m_axi_wready = 0;
-reg [ID_WIDTH-1:0] m_axi_bid = 0;
-reg [1:0] m_axi_bresp = 0;
-reg [BUSER_WIDTH-1:0] m_axi_buser = 0;
-reg m_axi_bvalid = 0;
-
-// Outputs
-wire s_axi_awready;
-wire s_axi_wready;
-wire [ID_WIDTH-1:0] s_axi_bid;
-wire [1:0] s_axi_bresp;
-wire [BUSER_WIDTH-1:0] s_axi_buser;
-wire s_axi_bvalid;
-wire [ID_WIDTH-1:0] m_axi_awid;
-wire [ADDR_WIDTH-1:0] m_axi_awaddr;
-wire [7:0] m_axi_awlen;
-wire [2:0] m_axi_awsize;
-wire [1:0] m_axi_awburst;
-wire m_axi_awlock;
-wire [3:0] m_axi_awcache;
-wire [2:0] m_axi_awprot;
-wire [3:0] m_axi_awqos;
-wire [3:0] m_axi_awregion;
-wire [AWUSER_WIDTH-1:0] m_axi_awuser;
-wire m_axi_awvalid;
-wire [DATA_WIDTH-1:0] m_axi_wdata;
-wire [STRB_WIDTH-1:0] m_axi_wstrb;
-wire m_axi_wlast;
-wire [WUSER_WIDTH-1:0] m_axi_wuser;
-wire m_axi_wvalid;
-wire m_axi_bready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axi_awid,
-        s_axi_awaddr,
-        s_axi_awlen,
-        s_axi_awsize,
-        s_axi_awburst,
-        s_axi_awlock,
-        s_axi_awcache,
-        s_axi_awprot,
-        s_axi_awqos,
-        s_axi_awregion,
-        s_axi_awuser,
-        s_axi_awvalid,
-        s_axi_wdata,
-        s_axi_wstrb,
-        s_axi_wlast,
-        s_axi_wuser,
-        s_axi_wvalid,
-        s_axi_bready,
-        m_axi_awready,
-        m_axi_wready,
-        m_axi_bid,
-        m_axi_bresp,
-        m_axi_buser,
-        m_axi_bvalid
-    );
-    $to_myhdl(
-        s_axi_awready,
-        s_axi_wready,
-        s_axi_bid,
-        s_axi_bresp,
-        s_axi_buser,
-        s_axi_bvalid,
-        m_axi_awid,
-        m_axi_awaddr,
-        m_axi_awlen,
-        m_axi_awsize,
-        m_axi_awburst,
-        m_axi_awlock,
-        m_axi_awcache,
-        m_axi_awprot,
-        m_axi_awqos,
-        m_axi_awregion,
-        m_axi_awuser,
-        m_axi_awvalid,
-        m_axi_wdata,
-        m_axi_wstrb,
-        m_axi_wlast,
-        m_axi_wuser,
-        m_axi_wvalid,
-        m_axi_bready
-    );
-
-    // dump file
-    $dumpfile("test_axi_fifo_wr_delay.lxt");
-    $dumpvars(0, test_axi_fifo_wr_delay);
-end
-
-axi_fifo_wr #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .ID_WIDTH(ID_WIDTH),
-    .AWUSER_ENABLE(AWUSER_ENABLE),
-    .AWUSER_WIDTH(AWUSER_WIDTH),
-    .WUSER_ENABLE(WUSER_ENABLE),
-    .WUSER_WIDTH(WUSER_WIDTH),
-    .BUSER_ENABLE(BUSER_ENABLE),
-    .BUSER_WIDTH(BUSER_WIDTH),
-    .FIFO_DEPTH(FIFO_DEPTH),
-    .FIFO_DELAY(FIFO_DELAY)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awregion(s_axi_awregion),
-    .s_axi_awuser(s_axi_awuser),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(s_axi_wuser),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(s_axi_buser),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .m_axi_awid(m_axi_awid),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(m_axi_awlen),
-    .m_axi_awsize(m_axi_awsize),
-    .m_axi_awburst(m_axi_awburst),
-    .m_axi_awlock(m_axi_awlock),
-    .m_axi_awcache(m_axi_awcache),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awqos(m_axi_awqos),
-    .m_axi_awregion(m_axi_awregion),
-    .m_axi_awuser(m_axi_awuser),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(m_axi_wlast),
-    .m_axi_wuser(m_axi_wuser),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(m_axi_bid),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(m_axi_buser),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready)
-);
-
-endmodule
diff --git a/tb/test_axi_register_rd.py b/tb/test_axi_register_rd.py
deleted file mode 100755
index c8490e7..0000000
--- a/tb/test_axi_register_rd.py
+++ /dev/null
@@ -1,305 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axi
-
-module = 'axi_register_rd'
-testbench = 'test_%s' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    ID_WIDTH = 8
-    ARUSER_ENABLE = 0
-    ARUSER_WIDTH = 1
-    RUSER_ENABLE = 0
-    RUSER_WIDTH = 1
-    AR_REG_TYPE = 1
-    R_REG_TYPE = 2
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axi_arid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axi_arlen = Signal(intbv(0)[8:])
-    s_axi_arsize = Signal(intbv(0)[3:])
-    s_axi_arburst = Signal(intbv(0)[2:])
-    s_axi_arlock = Signal(bool(0))
-    s_axi_arcache = Signal(intbv(0)[4:])
-    s_axi_arprot = Signal(intbv(0)[3:])
-    s_axi_arqos = Signal(intbv(0)[4:])
-    s_axi_arregion = Signal(intbv(0)[4:])
-    s_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
-    s_axi_arvalid = Signal(bool(0))
-    s_axi_rready = Signal(bool(0))
-    m_axi_arready = Signal(bool(0))
-    m_axi_rid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axi_rresp = Signal(intbv(0)[2:])
-    m_axi_rlast = Signal(bool(0))
-    m_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
-    m_axi_rvalid = Signal(bool(0))
-
-    # Outputs
-    s_axi_arready = Signal(bool(0))
-    s_axi_rid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axi_rresp = Signal(intbv(0)[2:])
-    s_axi_rlast = Signal(bool(0))
-    s_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
-    s_axi_rvalid = Signal(bool(0))
-    m_axi_arid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axi_arlen = Signal(intbv(0)[8:])
-    m_axi_arsize = Signal(intbv(0)[3:])
-    m_axi_arburst = Signal(intbv(0)[2:])
-    m_axi_arlock = Signal(bool(0))
-    m_axi_arcache = Signal(intbv(0)[4:])
-    m_axi_arprot = Signal(intbv(0)[3:])
-    m_axi_arqos = Signal(intbv(0)[4:])
-    m_axi_arregion = Signal(intbv(0)[4:])
-    m_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
-    m_axi_arvalid = Signal(bool(0))
-    m_axi_rready = Signal(bool(0))
-
-    # AXI4 master
-    axi_master_inst = axi.AXIMaster()
-    axi_master_pause = Signal(bool(False))
-
-    axi_master_logic = axi_master_inst.create_logic(
-        clk,
-        rst,
-        m_axi_arid=s_axi_arid,
-        m_axi_araddr=s_axi_araddr,
-        m_axi_arlen=s_axi_arlen,
-        m_axi_arsize=s_axi_arsize,
-        m_axi_arburst=s_axi_arburst,
-        m_axi_arlock=s_axi_arlock,
-        m_axi_arcache=s_axi_arcache,
-        m_axi_arprot=s_axi_arprot,
-        m_axi_arqos=s_axi_arqos,
-        m_axi_arregion=s_axi_arregion,
-        m_axi_arvalid=s_axi_arvalid,
-        m_axi_arready=s_axi_arready,
-        m_axi_rid=s_axi_rid,
-        m_axi_rdata=s_axi_rdata,
-        m_axi_rresp=s_axi_rresp,
-        m_axi_rlast=s_axi_rlast,
-        m_axi_rvalid=s_axi_rvalid,
-        m_axi_rready=s_axi_rready,
-        pause=axi_master_pause,
-        name='master'
-    )
-
-    # AXI4 RAM model
-    axi_ram_inst = axi.AXIRam(2**16)
-    axi_ram_pause = Signal(bool(False))
-
-    axi_ram_port0 = axi_ram_inst.create_port(
-        clk,
-        s_axi_arid=m_axi_arid,
-        s_axi_araddr=m_axi_araddr,
-        s_axi_arlen=m_axi_arlen,
-        s_axi_arsize=m_axi_arsize,
-        s_axi_arburst=m_axi_arburst,
-        s_axi_arlock=m_axi_arlock,
-        s_axi_arcache=m_axi_arcache,
-        s_axi_arprot=m_axi_arprot,
-        s_axi_arvalid=m_axi_arvalid,
-        s_axi_arready=m_axi_arready,
-        s_axi_rid=m_axi_rid,
-        s_axi_rdata=m_axi_rdata,
-        s_axi_rresp=m_axi_rresp,
-        s_axi_rlast=m_axi_rlast,
-        s_axi_rvalid=m_axi_rvalid,
-        s_axi_rready=m_axi_rready,
-        pause=axi_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axi_arid=s_axi_arid,
-        s_axi_araddr=s_axi_araddr,
-        s_axi_arlen=s_axi_arlen,
-        s_axi_arsize=s_axi_arsize,
-        s_axi_arburst=s_axi_arburst,
-        s_axi_arlock=s_axi_arlock,
-        s_axi_arcache=s_axi_arcache,
-        s_axi_arprot=s_axi_arprot,
-        s_axi_arqos=s_axi_arqos,
-        s_axi_arregion=s_axi_arregion,
-        s_axi_aruser=s_axi_aruser,
-        s_axi_arvalid=s_axi_arvalid,
-        s_axi_arready=s_axi_arready,
-        s_axi_rid=s_axi_rid,
-        s_axi_rdata=s_axi_rdata,
-        s_axi_rresp=s_axi_rresp,
-        s_axi_rlast=s_axi_rlast,
-        s_axi_ruser=s_axi_ruser,
-        s_axi_rvalid=s_axi_rvalid,
-        s_axi_rready=s_axi_rready,
-        m_axi_arid=m_axi_arid,
-        m_axi_araddr=m_axi_araddr,
-        m_axi_arlen=m_axi_arlen,
-        m_axi_arsize=m_axi_arsize,
-        m_axi_arburst=m_axi_arburst,
-        m_axi_arlock=m_axi_arlock,
-        m_axi_arcache=m_axi_arcache,
-        m_axi_arprot=m_axi_arprot,
-        m_axi_arqos=m_axi_arqos,
-        m_axi_arregion=m_axi_arregion,
-        m_axi_aruser=m_axi_aruser,
-        m_axi_arvalid=m_axi_arvalid,
-        m_axi_arready=m_axi_arready,
-        m_axi_rid=m_axi_rid,
-        m_axi_rdata=m_axi_rdata,
-        m_axi_rresp=m_axi_rresp,
-        m_axi_rlast=m_axi_rlast,
-        m_axi_ruser=m_axi_ruser,
-        m_axi_rvalid=m_axi_rvalid,
-        m_axi_rready=m_axi_rready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axi_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axi_master_inst.idle():
-            axi_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axi_master_inst.idle():
-            axi_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: read")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axi_ram_inst.write_mem(addr, test_data)
-
-        axi_master_inst.init_read(addr, len(test_data))
-
-        yield axi_master_inst.wait()
-        yield clk.posedge
-
-        data = axi_master_inst.get_read_data()
-        assert data[0] == addr
-        assert data[1] == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 2: various reads")
-        current_test.next = 2
-
-        for length in list(range(1,8))+[1024]:
-            for offset in list(range(4,8))+[4096-4]:
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    #addr = 256*(16*offset+length)+offset
-                    addr = offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axi_ram_inst.write_mem(addr, test_data)
-
-                    axi_master_inst.init_read(addr, length)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axi_master_inst.get_read_data()
-                    assert data[0] == addr
-                    assert data[1] == test_data
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axi_register_rd.v b/tb/test_axi_register_rd.v
deleted file mode 100644
index 6807afb..0000000
--- a/tb/test_axi_register_rd.v
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axi_register_rd
- */
-module test_axi_register_rd;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter ID_WIDTH = 8;
-parameter ARUSER_ENABLE = 0;
-parameter ARUSER_WIDTH = 1;
-parameter RUSER_ENABLE = 0;
-parameter RUSER_WIDTH = 1;
-parameter AR_REG_TYPE = 1;
-parameter R_REG_TYPE = 2;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ID_WIDTH-1:0] s_axi_arid = 0;
-reg [ADDR_WIDTH-1:0] s_axi_araddr = 0;
-reg [7:0] s_axi_arlen = 0;
-reg [2:0] s_axi_arsize = 0;
-reg [1:0] s_axi_arburst = 0;
-reg s_axi_arlock = 0;
-reg [3:0] s_axi_arcache = 0;
-reg [2:0] s_axi_arprot = 0;
-reg [3:0] s_axi_arqos = 0;
-reg [3:0] s_axi_arregion = 0;
-reg [ARUSER_WIDTH-1:0] s_axi_aruser = 0;
-reg s_axi_arvalid = 0;
-reg s_axi_rready = 0;
-reg m_axi_arready = 0;
-reg [ID_WIDTH-1:0] m_axi_rid = 0;
-reg [DATA_WIDTH-1:0] m_axi_rdata = 0;
-reg [1:0] m_axi_rresp = 0;
-reg m_axi_rlast = 0;
-reg [RUSER_WIDTH-1:0] m_axi_ruser = 0;
-reg m_axi_rvalid = 0;
-
-// Outputs
-wire s_axi_arready;
-wire [ID_WIDTH-1:0] s_axi_rid;
-wire [DATA_WIDTH-1:0] s_axi_rdata;
-wire [1:0] s_axi_rresp;
-wire s_axi_rlast;
-wire [RUSER_WIDTH-1:0] s_axi_ruser;
-wire s_axi_rvalid;
-wire [ID_WIDTH-1:0] m_axi_arid;
-wire [ADDR_WIDTH-1:0] m_axi_araddr;
-wire [7:0] m_axi_arlen;
-wire [2:0] m_axi_arsize;
-wire [1:0] m_axi_arburst;
-wire m_axi_arlock;
-wire [3:0] m_axi_arcache;
-wire [2:0] m_axi_arprot;
-wire [3:0] m_axi_arqos;
-wire [3:0] m_axi_arregion;
-wire [ARUSER_WIDTH-1:0] m_axi_aruser;
-wire m_axi_arvalid;
-wire m_axi_rready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axi_arid,
-        s_axi_araddr,
-        s_axi_arlen,
-        s_axi_arsize,
-        s_axi_arburst,
-        s_axi_arlock,
-        s_axi_arcache,
-        s_axi_arprot,
-        s_axi_arqos,
-        s_axi_arregion,
-        s_axi_aruser,
-        s_axi_arvalid,
-        s_axi_rready,
-        m_axi_arready,
-        m_axi_rid,
-        m_axi_rdata,
-        m_axi_rresp,
-        m_axi_rlast,
-        m_axi_ruser,
-        m_axi_rvalid
-    );
-    $to_myhdl(
-        s_axi_arready,
-        s_axi_rid,
-        s_axi_rdata,
-        s_axi_rresp,
-        s_axi_rlast,
-        s_axi_ruser,
-        s_axi_rvalid,
-        m_axi_arid,
-        m_axi_araddr,
-        m_axi_arlen,
-        m_axi_arsize,
-        m_axi_arburst,
-        m_axi_arlock,
-        m_axi_arcache,
-        m_axi_arprot,
-        m_axi_arqos,
-        m_axi_arregion,
-        m_axi_aruser,
-        m_axi_arvalid,
-        m_axi_rready
-    );
-
-    // dump file
-    $dumpfile("test_axi_register_rd.lxt");
-    $dumpvars(0, test_axi_register_rd);
-end
-
-axi_register_rd #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .ID_WIDTH(ID_WIDTH),
-    .ARUSER_ENABLE(ARUSER_ENABLE),
-    .ARUSER_WIDTH(ARUSER_WIDTH),
-    .RUSER_ENABLE(RUSER_ENABLE),
-    .RUSER_WIDTH(RUSER_WIDTH),
-    .AR_REG_TYPE(AR_REG_TYPE),
-    .R_REG_TYPE(R_REG_TYPE)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arqos(s_axi_arqos),
-    .s_axi_arregion(s_axi_arregion),
-    .s_axi_aruser(s_axi_aruser),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(s_axi_ruser),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .m_axi_arid(m_axi_arid),
-    .m_axi_araddr(m_axi_araddr),
-    .m_axi_arlen(m_axi_arlen),
-    .m_axi_arsize(m_axi_arsize),
-    .m_axi_arburst(m_axi_arburst),
-    .m_axi_arlock(m_axi_arlock),
-    .m_axi_arcache(m_axi_arcache),
-    .m_axi_arprot(m_axi_arprot),
-    .m_axi_arqos(m_axi_arqos),
-    .m_axi_arregion(m_axi_arregion),
-    .m_axi_aruser(m_axi_aruser),
-    .m_axi_arvalid(m_axi_arvalid),
-    .m_axi_arready(m_axi_arready),
-    .m_axi_rid(m_axi_rid),
-    .m_axi_rdata(m_axi_rdata),
-    .m_axi_rresp(m_axi_rresp),
-    .m_axi_rlast(m_axi_rlast),
-    .m_axi_ruser(m_axi_ruser),
-    .m_axi_rvalid(m_axi_rvalid),
-    .m_axi_rready(m_axi_rready)
-);
-
-endmodule
diff --git a/tb/test_axi_register_wr.py b/tb/test_axi_register_wr.py
deleted file mode 100755
index 0031b26..0000000
--- a/tb/test_axi_register_wr.py
+++ /dev/null
@@ -1,333 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axi
-
-module = 'axi_register_wr'
-testbench = 'test_%s' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    ID_WIDTH = 8
-    AWUSER_ENABLE = 0
-    AWUSER_WIDTH = 1
-    WUSER_ENABLE = 0
-    WUSER_WIDTH = 1
-    BUSER_ENABLE = 0
-    BUSER_WIDTH = 1
-    AW_REG_TYPE = 1
-    W_REG_TYPE = 2
-    B_REG_TYPE = 1
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axi_awid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axi_awlen = Signal(intbv(0)[8:])
-    s_axi_awsize = Signal(intbv(0)[3:])
-    s_axi_awburst = Signal(intbv(0)[2:])
-    s_axi_awlock = Signal(bool(0))
-    s_axi_awcache = Signal(intbv(0)[4:])
-    s_axi_awprot = Signal(intbv(0)[3:])
-    s_axi_awqos = Signal(intbv(0)[4:])
-    s_axi_awregion = Signal(intbv(0)[4:])
-    s_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
-    s_axi_awvalid = Signal(bool(0))
-    s_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    s_axi_wlast = Signal(bool(0))
-    s_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
-    s_axi_wvalid = Signal(bool(0))
-    s_axi_bready = Signal(bool(0))
-    m_axi_awready = Signal(bool(0))
-    m_axi_wready = Signal(bool(0))
-    m_axi_bid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_bresp = Signal(intbv(0)[2:])
-    m_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
-    m_axi_bvalid = Signal(bool(0))
-
-    # Outputs
-    s_axi_awready = Signal(bool(0))
-    s_axi_wready = Signal(bool(0))
-    s_axi_bid = Signal(intbv(0)[ID_WIDTH:])
-    s_axi_bresp = Signal(intbv(0)[2:])
-    s_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
-    s_axi_bvalid = Signal(bool(0))
-    m_axi_awid = Signal(intbv(0)[ID_WIDTH:])
-    m_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axi_awlen = Signal(intbv(0)[8:])
-    m_axi_awsize = Signal(intbv(0)[3:])
-    m_axi_awburst = Signal(intbv(0)[2:])
-    m_axi_awlock = Signal(bool(0))
-    m_axi_awcache = Signal(intbv(0)[4:])
-    m_axi_awprot = Signal(intbv(0)[3:])
-    m_axi_awqos = Signal(intbv(0)[4:])
-    m_axi_awregion = Signal(intbv(0)[4:])
-    m_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
-    m_axi_awvalid = Signal(bool(0))
-    m_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    m_axi_wlast = Signal(bool(0))
-    m_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
-    m_axi_wvalid = Signal(bool(0))
-    m_axi_bready = Signal(bool(0))
-
-    # AXI4 master
-    axi_master_inst = axi.AXIMaster()
-    axi_master_pause = Signal(bool(False))
-
-    axi_master_logic = axi_master_inst.create_logic(
-        clk,
-        rst,
-        m_axi_awid=s_axi_awid,
-        m_axi_awaddr=s_axi_awaddr,
-        m_axi_awlen=s_axi_awlen,
-        m_axi_awsize=s_axi_awsize,
-        m_axi_awburst=s_axi_awburst,
-        m_axi_awlock=s_axi_awlock,
-        m_axi_awcache=s_axi_awcache,
-        m_axi_awprot=s_axi_awprot,
-        m_axi_awqos=s_axi_awqos,
-        m_axi_awregion=s_axi_awregion,
-        m_axi_awvalid=s_axi_awvalid,
-        m_axi_awready=s_axi_awready,
-        m_axi_wdata=s_axi_wdata,
-        m_axi_wstrb=s_axi_wstrb,
-        m_axi_wlast=s_axi_wlast,
-        m_axi_wvalid=s_axi_wvalid,
-        m_axi_wready=s_axi_wready,
-        m_axi_bid=s_axi_bid,
-        m_axi_bresp=s_axi_bresp,
-        m_axi_bvalid=s_axi_bvalid,
-        m_axi_bready=s_axi_bready,
-        pause=axi_master_pause,
-        name='master'
-    )
-
-    # AXI4 RAM model
-    axi_ram_inst = axi.AXIRam(2**16)
-    axi_ram_pause = Signal(bool(False))
-
-    axi_ram_port0 = axi_ram_inst.create_port(
-        clk,
-        s_axi_awid=m_axi_awid,
-        s_axi_awaddr=m_axi_awaddr,
-        s_axi_awlen=m_axi_awlen,
-        s_axi_awsize=m_axi_awsize,
-        s_axi_awburst=m_axi_awburst,
-        s_axi_awlock=m_axi_awlock,
-        s_axi_awcache=m_axi_awcache,
-        s_axi_awprot=m_axi_awprot,
-        s_axi_awvalid=m_axi_awvalid,
-        s_axi_awready=m_axi_awready,
-        s_axi_wdata=m_axi_wdata,
-        s_axi_wstrb=m_axi_wstrb,
-        s_axi_wlast=m_axi_wlast,
-        s_axi_wvalid=m_axi_wvalid,
-        s_axi_wready=m_axi_wready,
-        s_axi_bid=m_axi_bid,
-        s_axi_bresp=m_axi_bresp,
-        s_axi_bvalid=m_axi_bvalid,
-        s_axi_bready=m_axi_bready,
-        pause=axi_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axi_awid=s_axi_awid,
-        s_axi_awaddr=s_axi_awaddr,
-        s_axi_awlen=s_axi_awlen,
-        s_axi_awsize=s_axi_awsize,
-        s_axi_awburst=s_axi_awburst,
-        s_axi_awlock=s_axi_awlock,
-        s_axi_awcache=s_axi_awcache,
-        s_axi_awprot=s_axi_awprot,
-        s_axi_awqos=s_axi_awqos,
-        s_axi_awregion=s_axi_awregion,
-        s_axi_awuser=s_axi_awuser,
-        s_axi_awvalid=s_axi_awvalid,
-        s_axi_awready=s_axi_awready,
-        s_axi_wdata=s_axi_wdata,
-        s_axi_wstrb=s_axi_wstrb,
-        s_axi_wlast=s_axi_wlast,
-        s_axi_wuser=s_axi_wuser,
-        s_axi_wvalid=s_axi_wvalid,
-        s_axi_wready=s_axi_wready,
-        s_axi_bid=s_axi_bid,
-        s_axi_bresp=s_axi_bresp,
-        s_axi_buser=s_axi_buser,
-        s_axi_bvalid=s_axi_bvalid,
-        s_axi_bready=s_axi_bready,
-        m_axi_awid=m_axi_awid,
-        m_axi_awaddr=m_axi_awaddr,
-        m_axi_awlen=m_axi_awlen,
-        m_axi_awsize=m_axi_awsize,
-        m_axi_awburst=m_axi_awburst,
-        m_axi_awlock=m_axi_awlock,
-        m_axi_awcache=m_axi_awcache,
-        m_axi_awprot=m_axi_awprot,
-        m_axi_awqos=m_axi_awqos,
-        m_axi_awregion=m_axi_awregion,
-        m_axi_awuser=m_axi_awuser,
-        m_axi_awvalid=m_axi_awvalid,
-        m_axi_awready=m_axi_awready,
-        m_axi_wdata=m_axi_wdata,
-        m_axi_wstrb=m_axi_wstrb,
-        m_axi_wlast=m_axi_wlast,
-        m_axi_wuser=m_axi_wuser,
-        m_axi_wvalid=m_axi_wvalid,
-        m_axi_wready=m_axi_wready,
-        m_axi_bid=m_axi_bid,
-        m_axi_bresp=m_axi_bresp,
-        m_axi_buser=m_axi_buser,
-        m_axi_bvalid=m_axi_bvalid,
-        m_axi_bready=m_axi_bready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axi_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axi_master_inst.idle():
-            axi_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axi_master_inst.idle():
-            axi_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axi_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: write")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axi_master_inst.init_write(addr, test_data)
-
-        yield axi_master_inst.wait()
-        yield clk.posedge
-
-        data = axi_ram_inst.read_mem(addr&0xffffff80, 32)
-        for i in range(0, len(data), 16):
-            print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-        assert axi_ram_inst.read_mem(addr, len(test_data)) == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 2: various writes")
-        current_test.next = 2
-
-        for length in list(range(1,8))+[1024]:
-            for offset in list(range(4,8))+[4096-4]:
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    #addr = 256*(16*offset+length)+offset
-                    addr = offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axi_ram_inst.write_mem(addr&0xffffff80, b'\xAA'*(length+256))
-                    axi_master_inst.init_write(addr, test_data)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axi_ram_inst.read_mem(addr&0xffffff80, 32)
-                    for i in range(0, len(data), 16):
-                        print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-                    assert axi_ram_inst.read_mem(addr, length) == test_data
-                    assert axi_ram_inst.read_mem(addr-1, 1) == b'\xAA'
-                    assert axi_ram_inst.read_mem(addr+length, 1) == b'\xAA'
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axi_register_wr.v b/tb/test_axi_register_wr.v
deleted file mode 100644
index 5f27625..0000000
--- a/tb/test_axi_register_wr.v
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axi_register_wr
- */
-module test_axi_register_wr;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter ID_WIDTH = 8;
-parameter AWUSER_ENABLE = 0;
-parameter AWUSER_WIDTH = 1;
-parameter WUSER_ENABLE = 0;
-parameter WUSER_WIDTH = 1;
-parameter BUSER_ENABLE = 0;
-parameter BUSER_WIDTH = 1;
-parameter AW_REG_TYPE = 1;
-parameter W_REG_TYPE = 2;
-parameter B_REG_TYPE = 1;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ID_WIDTH-1:0] s_axi_awid = 0;
-reg [ADDR_WIDTH-1:0] s_axi_awaddr = 0;
-reg [7:0] s_axi_awlen = 0;
-reg [2:0] s_axi_awsize = 0;
-reg [1:0] s_axi_awburst = 0;
-reg s_axi_awlock = 0;
-reg [3:0] s_axi_awcache = 0;
-reg [2:0] s_axi_awprot = 0;
-reg [3:0] s_axi_awqos = 0;
-reg [3:0] s_axi_awregion = 0;
-reg [AWUSER_WIDTH-1:0] s_axi_awuser = 0;
-reg s_axi_awvalid = 0;
-reg [DATA_WIDTH-1:0] s_axi_wdata = 0;
-reg [STRB_WIDTH-1:0] s_axi_wstrb = 0;
-reg s_axi_wlast = 0;
-reg [WUSER_WIDTH-1:0] s_axi_wuser = 0;
-reg s_axi_wvalid = 0;
-reg s_axi_bready = 0;
-reg m_axi_awready = 0;
-reg m_axi_wready = 0;
-reg [ID_WIDTH-1:0] m_axi_bid = 0;
-reg [1:0] m_axi_bresp = 0;
-reg [BUSER_WIDTH-1:0] m_axi_buser = 0;
-reg m_axi_bvalid = 0;
-
-// Outputs
-wire s_axi_awready;
-wire s_axi_wready;
-wire [ID_WIDTH-1:0] s_axi_bid;
-wire [1:0] s_axi_bresp;
-wire [BUSER_WIDTH-1:0] s_axi_buser;
-wire s_axi_bvalid;
-wire [ID_WIDTH-1:0] m_axi_awid;
-wire [ADDR_WIDTH-1:0] m_axi_awaddr;
-wire [7:0] m_axi_awlen;
-wire [2:0] m_axi_awsize;
-wire [1:0] m_axi_awburst;
-wire m_axi_awlock;
-wire [3:0] m_axi_awcache;
-wire [2:0] m_axi_awprot;
-wire [3:0] m_axi_awqos;
-wire [3:0] m_axi_awregion;
-wire [AWUSER_WIDTH-1:0] m_axi_awuser;
-wire m_axi_awvalid;
-wire [DATA_WIDTH-1:0] m_axi_wdata;
-wire [STRB_WIDTH-1:0] m_axi_wstrb;
-wire m_axi_wlast;
-wire [WUSER_WIDTH-1:0] m_axi_wuser;
-wire m_axi_wvalid;
-wire m_axi_bready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axi_awid,
-        s_axi_awaddr,
-        s_axi_awlen,
-        s_axi_awsize,
-        s_axi_awburst,
-        s_axi_awlock,
-        s_axi_awcache,
-        s_axi_awprot,
-        s_axi_awqos,
-        s_axi_awregion,
-        s_axi_awuser,
-        s_axi_awvalid,
-        s_axi_wdata,
-        s_axi_wstrb,
-        s_axi_wlast,
-        s_axi_wuser,
-        s_axi_wvalid,
-        s_axi_bready,
-        m_axi_awready,
-        m_axi_wready,
-        m_axi_bid,
-        m_axi_bresp,
-        m_axi_buser,
-        m_axi_bvalid
-    );
-    $to_myhdl(
-        s_axi_awready,
-        s_axi_wready,
-        s_axi_bid,
-        s_axi_bresp,
-        s_axi_buser,
-        s_axi_bvalid,
-        m_axi_awid,
-        m_axi_awaddr,
-        m_axi_awlen,
-        m_axi_awsize,
-        m_axi_awburst,
-        m_axi_awlock,
-        m_axi_awcache,
-        m_axi_awprot,
-        m_axi_awqos,
-        m_axi_awregion,
-        m_axi_awuser,
-        m_axi_awvalid,
-        m_axi_wdata,
-        m_axi_wstrb,
-        m_axi_wlast,
-        m_axi_wuser,
-        m_axi_wvalid,
-        m_axi_bready
-    );
-
-    // dump file
-    $dumpfile("test_axi_register_wr.lxt");
-    $dumpvars(0, test_axi_register_wr);
-end
-
-axi_register_wr #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .ID_WIDTH(ID_WIDTH),
-    .AWUSER_ENABLE(AWUSER_ENABLE),
-    .AWUSER_WIDTH(AWUSER_WIDTH),
-    .WUSER_ENABLE(WUSER_ENABLE),
-    .WUSER_WIDTH(WUSER_WIDTH),
-    .BUSER_ENABLE(BUSER_ENABLE),
-    .BUSER_WIDTH(BUSER_WIDTH),
-    .AW_REG_TYPE(AW_REG_TYPE),
-    .W_REG_TYPE(W_REG_TYPE),
-    .B_REG_TYPE(B_REG_TYPE)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awregion(s_axi_awregion),
-    .s_axi_awuser(s_axi_awuser),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(s_axi_wuser),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(s_axi_buser),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .m_axi_awid(m_axi_awid),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(m_axi_awlen),
-    .m_axi_awsize(m_axi_awsize),
-    .m_axi_awburst(m_axi_awburst),
-    .m_axi_awlock(m_axi_awlock),
-    .m_axi_awcache(m_axi_awcache),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awqos(m_axi_awqos),
-    .m_axi_awregion(m_axi_awregion),
-    .m_axi_awuser(m_axi_awuser),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(m_axi_wlast),
-    .m_axi_wuser(m_axi_wuser),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(m_axi_bid),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(m_axi_buser),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready)
-);
-
-endmodule
diff --git a/tb/test_axil_register_rd.py b/tb/test_axil_register_rd.py
deleted file mode 100755
index 9b0a6da..0000000
--- a/tb/test_axil_register_rd.py
+++ /dev/null
@@ -1,233 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axil
-
-module = 'axil_register_rd'
-testbench = 'test_%s' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    AR_REG_TYPE = 1
-    R_REG_TYPE = 1
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axil_arprot = Signal(intbv(0)[3:])
-    s_axil_arvalid = Signal(bool(0))
-    s_axil_rready = Signal(bool(0))
-    m_axil_arready = Signal(bool(0))
-    m_axil_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axil_rresp = Signal(intbv(0)[2:])
-    m_axil_rvalid = Signal(bool(0))
-
-    # Outputs
-    s_axil_arready = Signal(bool(0))
-    s_axil_rdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axil_rresp = Signal(intbv(0)[2:])
-    s_axil_rvalid = Signal(bool(0))
-    m_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axil_arprot = Signal(intbv(0)[3:])
-    m_axil_arvalid = Signal(bool(0))
-    m_axil_rready = Signal(bool(0))
-
-    # AXIl4 master
-    axil_master_inst = axil.AXILiteMaster()
-    axil_master_pause = Signal(bool(False))
-
-    axil_master_logic = axil_master_inst.create_logic(
-        clk,
-        rst,
-        m_axil_araddr=s_axil_araddr,
-        m_axil_arprot=s_axil_arprot,
-        m_axil_arvalid=s_axil_arvalid,
-        m_axil_arready=s_axil_arready,
-        m_axil_rdata=s_axil_rdata,
-        m_axil_rresp=s_axil_rresp,
-        m_axil_rvalid=s_axil_rvalid,
-        m_axil_rready=s_axil_rready,
-        pause=axil_master_pause,
-        name='master'
-    )
-
-    # AXIl4 RAM model
-    axil_ram_inst = axil.AXILiteRam(2**16)
-    axil_ram_pause = Signal(bool(False))
-
-    axil_ram_port0 = axil_ram_inst.create_port(
-        clk,
-        s_axil_araddr=m_axil_araddr,
-        s_axil_arprot=m_axil_arprot,
-        s_axil_arvalid=m_axil_arvalid,
-        s_axil_arready=m_axil_arready,
-        s_axil_rdata=m_axil_rdata,
-        s_axil_rresp=m_axil_rresp,
-        s_axil_rvalid=m_axil_rvalid,
-        s_axil_rready=m_axil_rready,
-        pause=axil_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axil_araddr=s_axil_araddr,
-        s_axil_arprot=s_axil_arprot,
-        s_axil_arvalid=s_axil_arvalid,
-        s_axil_arready=s_axil_arready,
-        s_axil_rdata=s_axil_rdata,
-        s_axil_rresp=s_axil_rresp,
-        s_axil_rvalid=s_axil_rvalid,
-        s_axil_rready=s_axil_rready,
-        m_axil_araddr=m_axil_araddr,
-        m_axil_arprot=m_axil_arprot,
-        m_axil_arvalid=m_axil_arvalid,
-        m_axil_arready=m_axil_arready,
-        m_axil_rdata=m_axil_rdata,
-        m_axil_rresp=m_axil_rresp,
-        m_axil_rvalid=m_axil_rvalid,
-        m_axil_rready=m_axil_rready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axil_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axil_master_inst.idle():
-            axil_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axil_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axil_master_inst.idle():
-            axil_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axil_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: read")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axil_ram_inst.write_mem(addr, test_data)
-
-        axil_master_inst.init_read(addr, len(test_data))
-
-        yield axil_master_inst.wait()
-        yield clk.posedge
-
-        data = axil_master_inst.get_read_data()
-        assert data[0] == addr
-        assert data[1] == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 2: various reads")
-        current_test.next = 2
-
-        for length in range(1,8):
-            for offset in range(4,8):
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    addr = 256*(16*offset+length)+offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axil_ram_inst.write_mem(addr, test_data)
-
-                    axil_master_inst.init_read(addr, length)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axil_master_inst.get_read_data()
-                    assert data[0] == addr
-                    assert data[1] == test_data
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axil_register_rd.v b/tb/test_axil_register_rd.v
deleted file mode 100644
index d76bafd..0000000
--- a/tb/test_axil_register_rd.v
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axil_register_rd
- */
-module test_axil_register_rd;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter AR_REG_TYPE = 1;
-parameter R_REG_TYPE = 1;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ADDR_WIDTH-1:0] s_axil_araddr = 0;
-reg [2:0] s_axil_arprot = 0;
-reg s_axil_arvalid = 0;
-reg s_axil_rready = 0;
-reg m_axil_arready = 0;
-reg [DATA_WIDTH-1:0] m_axil_rdata = 0;
-reg [1:0] m_axil_rresp = 0;
-reg m_axil_rvalid = 0;
-
-// Outputs
-wire s_axil_arready;
-wire [DATA_WIDTH-1:0] s_axil_rdata;
-wire [1:0] s_axil_rresp;
-wire s_axil_rvalid;
-wire [ADDR_WIDTH-1:0] m_axil_araddr;
-wire [2:0] m_axil_arprot;
-wire m_axil_arvalid;
-wire m_axil_rready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axil_araddr,
-        s_axil_arprot,
-        s_axil_arvalid,
-        s_axil_rready,
-        m_axil_arready,
-        m_axil_rdata,
-        m_axil_rresp,
-        m_axil_rvalid
-    );
-    $to_myhdl(
-        s_axil_arready,
-        s_axil_rdata,
-        s_axil_rresp,
-        s_axil_rvalid,
-        m_axil_araddr,
-        m_axil_arprot,
-        m_axil_arvalid,
-        m_axil_rready
-    );
-
-    // dump file
-    $dumpfile("test_axil_register_rd.lxt");
-    $dumpvars(0, test_axil_register_rd);
-end
-
-axil_register_rd #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .AR_REG_TYPE(AR_REG_TYPE),
-    .R_REG_TYPE(R_REG_TYPE)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axil_araddr(s_axil_araddr),
-    .s_axil_arprot(s_axil_arprot),
-    .s_axil_arvalid(s_axil_arvalid),
-    .s_axil_arready(s_axil_arready),
-    .s_axil_rdata(s_axil_rdata),
-    .s_axil_rresp(s_axil_rresp),
-    .s_axil_rvalid(s_axil_rvalid),
-    .s_axil_rready(s_axil_rready),
-    .m_axil_araddr(m_axil_araddr),
-    .m_axil_arprot(m_axil_arprot),
-    .m_axil_arvalid(m_axil_arvalid),
-    .m_axil_arready(m_axil_arready),
-    .m_axil_rdata(m_axil_rdata),
-    .m_axil_rresp(m_axil_rresp),
-    .m_axil_rvalid(m_axil_rvalid),
-    .m_axil_rready(m_axil_rready)
-);
-
-endmodule
diff --git a/tb/test_axil_register_wr.py b/tb/test_axil_register_wr.py
deleted file mode 100755
index 52a7793..0000000
--- a/tb/test_axil_register_wr.py
+++ /dev/null
@@ -1,255 +0,0 @@
-#!/usr/bin/env python
-"""
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-"""
-
-from myhdl import *
-import os
-
-import axil
-
-module = 'axil_register_wr'
-testbench = 'test_%s' % module
-
-srcs = []
-
-srcs.append("../rtl/%s.v" % module)
-srcs.append("%s.v" % testbench)
-
-src = ' '.join(srcs)
-
-build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
-
-def bench():
-
-    # Parameters
-    DATA_WIDTH = 32
-    ADDR_WIDTH = 16
-    STRB_WIDTH = (DATA_WIDTH/8)
-    AW_REG_TYPE = 1
-    W_REG_TYPE = 1
-    B_REG_TYPE = 1
-
-    # Inputs
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    current_test = Signal(intbv(0)[8:])
-
-    s_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    s_axil_awprot = Signal(intbv(0)[3:])
-    s_axil_awvalid = Signal(bool(0))
-    s_axil_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    s_axil_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    s_axil_wvalid = Signal(bool(0))
-    s_axil_bready = Signal(bool(0))
-    m_axil_awready = Signal(bool(0))
-    m_axil_wready = Signal(bool(0))
-    m_axil_bresp = Signal(intbv(0)[2:])
-    m_axil_bvalid = Signal(bool(0))
-
-    # Outputs
-    s_axil_awready = Signal(bool(0))
-    s_axil_wready = Signal(bool(0))
-    s_axil_bresp = Signal(intbv(0)[2:])
-    s_axil_bvalid = Signal(bool(0))
-    m_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
-    m_axil_awprot = Signal(intbv(0)[3:])
-    m_axil_awvalid = Signal(bool(0))
-    m_axil_wdata = Signal(intbv(0)[DATA_WIDTH:])
-    m_axil_wstrb = Signal(intbv(0)[STRB_WIDTH:])
-    m_axil_wvalid = Signal(bool(0))
-    m_axil_bready = Signal(bool(0))
-
-    # AXIl4 master
-    axil_master_inst = axil.AXILiteMaster()
-    axil_master_pause = Signal(bool(False))
-
-    axil_master_logic = axil_master_inst.create_logic(
-        clk,
-        rst,
-        m_axil_awaddr=s_axil_awaddr,
-        m_axil_awprot=s_axil_awprot,
-        m_axil_awvalid=s_axil_awvalid,
-        m_axil_awready=s_axil_awready,
-        m_axil_wdata=s_axil_wdata,
-        m_axil_wstrb=s_axil_wstrb,
-        m_axil_wvalid=s_axil_wvalid,
-        m_axil_wready=s_axil_wready,
-        m_axil_bresp=s_axil_bresp,
-        m_axil_bvalid=s_axil_bvalid,
-        m_axil_bready=s_axil_bready,
-        pause=axil_master_pause,
-        name='master'
-    )
-
-    # AXIl4 RAM model
-    axil_ram_inst = axil.AXILiteRam(2**16)
-    axil_ram_pause = Signal(bool(False))
-
-    axil_ram_port0 = axil_ram_inst.create_port(
-        clk,
-        s_axil_awaddr=m_axil_awaddr,
-        s_axil_awprot=m_axil_awprot,
-        s_axil_awvalid=m_axil_awvalid,
-        s_axil_awready=m_axil_awready,
-        s_axil_wdata=m_axil_wdata,
-        s_axil_wstrb=m_axil_wstrb,
-        s_axil_wvalid=m_axil_wvalid,
-        s_axil_wready=m_axil_wready,
-        s_axil_bresp=m_axil_bresp,
-        s_axil_bvalid=m_axil_bvalid,
-        s_axil_bready=m_axil_bready,
-        pause=axil_ram_pause,
-        name='port0'
-    )
-
-    # DUT
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,
-        current_test=current_test,
-        s_axil_awaddr=s_axil_awaddr,
-        s_axil_awprot=s_axil_awprot,
-        s_axil_awvalid=s_axil_awvalid,
-        s_axil_awready=s_axil_awready,
-        s_axil_wdata=s_axil_wdata,
-        s_axil_wstrb=s_axil_wstrb,
-        s_axil_wvalid=s_axil_wvalid,
-        s_axil_wready=s_axil_wready,
-        s_axil_bresp=s_axil_bresp,
-        s_axil_bvalid=s_axil_bvalid,
-        s_axil_bready=s_axil_bready,
-        m_axil_awaddr=m_axil_awaddr,
-        m_axil_awprot=m_axil_awprot,
-        m_axil_awvalid=m_axil_awvalid,
-        m_axil_awready=m_axil_awready,
-        m_axil_wdata=m_axil_wdata,
-        m_axil_wstrb=m_axil_wstrb,
-        m_axil_wvalid=m_axil_wvalid,
-        m_axil_wready=m_axil_wready,
-        m_axil_bresp=m_axil_bresp,
-        m_axil_bvalid=m_axil_bvalid,
-        m_axil_bready=m_axil_bready
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    def wait_normal():
-        while not axil_master_inst.idle():
-            yield clk.posedge
-
-    def wait_pause_master():
-        while not axil_master_inst.idle():
-            axil_master_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axil_master_pause.next = False
-            yield clk.posedge
-
-    def wait_pause_slave():
-        while not axil_master_inst.idle():
-            axil_ram_pause.next = True
-            yield clk.posedge
-            yield clk.posedge
-            yield clk.posedge
-            axil_ram_pause.next = False
-            yield clk.posedge
-
-    @instance
-    def check():
-        yield delay(100)
-        yield clk.posedge
-        rst.next = 1
-        yield clk.posedge
-        rst.next = 0
-        yield clk.posedge
-        yield delay(100)
-        yield clk.posedge
-
-        # testbench stimulus
-
-        yield clk.posedge
-        print("test 1: write")
-        current_test.next = 1
-
-        addr = 4
-        test_data = b'\x11\x22\x33\x44'
-
-        axil_master_inst.init_write(addr, test_data)
-
-        yield axil_master_inst.wait()
-        yield clk.posedge
-
-        data = axil_ram_inst.read_mem(addr&0xffffff80, 32)
-        for i in range(0, len(data), 16):
-            print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-        assert axil_ram_inst.read_mem(addr, len(test_data)) == test_data
-
-        yield delay(100)
-
-        yield clk.posedge
-        print("test 3: various writes")
-        current_test.next = 3
-
-        for length in range(1,8):
-            for offset in range(4,8):
-                for wait in wait_normal, wait_pause_master, wait_pause_slave:
-                    print("length %d, offset %d"% (length, offset))
-                    addr = 256*(16*offset+length)+offset
-                    test_data = bytearray([x%256 for x in range(length)])
-
-                    axil_ram_inst.write_mem(addr&0xffffff80, b'\xAA'*(length+256))
-                    axil_master_inst.init_write(addr, test_data)
-
-                    yield wait()
-                    yield clk.posedge
-
-                    data = axil_ram_inst.read_mem(addr&0xffffff80, 32)
-                    for i in range(0, len(data), 16):
-                        print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
-
-                    assert axil_ram_inst.read_mem(addr, length) == test_data
-                    assert axil_ram_inst.read_mem(addr-1, 1) == b'\xAA'
-                    assert axil_ram_inst.read_mem(addr+length, 1) == b'\xAA'
-
-        yield delay(100)
-
-        raise StopSimulation
-
-    return instances()
-
-def test_bench():
-    sim = Simulation(bench())
-    sim.run()
-
-if __name__ == '__main__':
-    print("Running test...")
-    test_bench()
diff --git a/tb/test_axil_register_wr.v b/tb/test_axil_register_wr.v
deleted file mode 100644
index 1ecd27a..0000000
--- a/tb/test_axil_register_wr.v
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
-
-Copyright (c) 2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`timescale 1ns / 1ps
-
-/*
- * Testbench for axil_register_wr
- */
-module test_axil_register_wr;
-
-// Parameters
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 16;
-parameter STRB_WIDTH = (DATA_WIDTH/8);
-parameter AW_REG_TYPE = 1;
-parameter W_REG_TYPE = 1;
-parameter B_REG_TYPE = 1;
-
-// Inputs
-reg clk = 0;
-reg rst = 0;
-reg [7:0] current_test = 0;
-
-reg [ADDR_WIDTH-1:0] s_axil_awaddr = 0;
-reg [2:0] s_axil_awprot = 0;
-reg s_axil_awvalid = 0;
-reg [DATA_WIDTH-1:0] s_axil_wdata = 0;
-reg [STRB_WIDTH-1:0] s_axil_wstrb = 0;
-reg s_axil_wvalid = 0;
-reg s_axil_bready = 0;
-reg m_axil_awready = 0;
-reg m_axil_wready = 0;
-reg [1:0] m_axil_bresp = 0;
-reg m_axil_bvalid = 0;
-
-// Outputs
-wire s_axil_awready;
-wire s_axil_wready;
-wire [1:0] s_axil_bresp;
-wire s_axil_bvalid;
-wire [ADDR_WIDTH-1:0] m_axil_awaddr;
-wire [2:0] m_axil_awprot;
-wire m_axil_awvalid;
-wire [DATA_WIDTH-1:0] m_axil_wdata;
-wire [STRB_WIDTH-1:0] m_axil_wstrb;
-wire m_axil_wvalid;
-wire m_axil_bready;
-
-initial begin
-    // myhdl integration
-    $from_myhdl(
-        clk,
-        rst,
-        current_test,
-        s_axil_awaddr,
-        s_axil_awprot,
-        s_axil_awvalid,
-        s_axil_wdata,
-        s_axil_wstrb,
-        s_axil_wvalid,
-        s_axil_bready,
-        m_axil_awready,
-        m_axil_wready,
-        m_axil_bresp,
-        m_axil_bvalid
-    );
-    $to_myhdl(
-        s_axil_awready,
-        s_axil_wready,
-        s_axil_bresp,
-        s_axil_bvalid,
-        m_axil_awaddr,
-        m_axil_awprot,
-        m_axil_awvalid,
-        m_axil_wdata,
-        m_axil_wstrb,
-        m_axil_wvalid,
-        m_axil_bready
-    );
-
-    // dump file
-    $dumpfile("test_axil_register_wr.lxt");
-    $dumpvars(0, test_axil_register_wr);
-end
-
-axil_register_wr #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .STRB_WIDTH(STRB_WIDTH),
-    .AW_REG_TYPE(AW_REG_TYPE),
-    .W_REG_TYPE(W_REG_TYPE),
-    .B_REG_TYPE(B_REG_TYPE)
-)
-UUT (
-    .clk(clk),
-    .rst(rst),
-    .s_axil_awaddr(s_axil_awaddr),
-    .s_axil_awprot(s_axil_awprot),
-    .s_axil_awvalid(s_axil_awvalid),
-    .s_axil_awready(s_axil_awready),
-    .s_axil_wdata(s_axil_wdata),
-    .s_axil_wstrb(s_axil_wstrb),
-    .s_axil_wvalid(s_axil_wvalid),
-    .s_axil_wready(s_axil_wready),
-    .s_axil_bresp(s_axil_bresp),
-    .s_axil_bvalid(s_axil_bvalid),
-    .s_axil_bready(s_axil_bready),
-    .m_axil_awaddr(m_axil_awaddr),
-    .m_axil_awprot(m_axil_awprot),
-    .m_axil_awvalid(m_axil_awvalid),
-    .m_axil_awready(m_axil_awready),
-    .m_axil_wdata(m_axil_wdata),
-    .m_axil_wstrb(m_axil_wstrb),
-    .m_axil_wvalid(m_axil_wvalid),
-    .m_axil_wready(m_axil_wready),
-    .m_axil_bresp(m_axil_bresp),
-    .m_axil_bvalid(m_axil_bvalid),
-    .m_axil_bready(m_axil_bready)
-);
-
-endmodule