mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-14 06:42:55 +08:00
Fix instance names in wrappers
This commit is contained in:
parent
9c4012f58d
commit
a852697707
@ -334,7 +334,7 @@ axi_crossbar #(
|
||||
.M_W_REG_TYPE({ {% for p in range(n-1,-1,-1) %}w_2(M{{'%02d'%p}}_W_REG_TYPE){% if not loop.last %}, {% endif %}{% endfor %} }),
|
||||
.M_B_REG_TYPE({ {% for p in range(n-1,-1,-1) %}w_2(M{{'%02d'%p}}_B_REG_TYPE){% if not loop.last %}, {% endif %}{% endfor %} })
|
||||
)
|
||||
UUT (
|
||||
axi_crossbar_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axi_awid({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axi_awid{% if not loop.last %}, {% endif %}{% endfor %} }),
|
||||
|
@ -173,7 +173,7 @@ axil_interconnect #(
|
||||
.M_CONNECT_WRITE({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT_WRITE){% if not loop.last %}, {% endif %}{% endfor %} }),
|
||||
.M_SECURE({ {% for p in range(n-1,-1,-1) %}w_1(M{{'%02d'%p}}_SECURE){% if not loop.last %}, {% endif %}{% endfor %} })
|
||||
)
|
||||
UUT (
|
||||
axil_interconnect_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axil_awaddr({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_awaddr{% if not loop.last %}, {% endif %}{% endfor %} }),
|
||||
|
Loading…
x
Reference in New Issue
Block a user