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Remove unnecessary reset

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Alex Forencich 2019-01-17 17:09:55 -08:00
parent 818fac5daa
commit b1f40411ad
1 changed files with 0 additions and 1 deletions
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rtl/axil_ram.v
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@ -164,7 +164,6 @@ end
always @(posedge clk) begin
if (rst) begin
s_axil_arready_reg <= 1'b0;
s_axil_rdata_reg <= {DATA_WIDTH{1'b0}};
s_axil_rresp_reg <= 2'b00;
s_axil_rvalid_reg <= 1'b0;
s_axil_rvalid_pipe_reg <= 1'b0;