diff --git a/rtl/axil_crossbar_rd.v b/rtl/axil_crossbar_rd.v
index 3586839..d8bf745 100644
--- a/rtl/axil_crossbar_rd.v
+++ b/rtl/axil_crossbar_rd.v
@@ -154,9 +154,14 @@ generate
         reg [CL_M_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0];
         (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
         reg fifo_decerr[(2**FIFO_ADDR_WIDTH)-1:0];
+
         wire [CL_M_COUNT-1:0] fifo_wr_select;
         wire fifo_wr_decerr;
         wire fifo_wr_en;
+
+        reg [CL_M_COUNT-1:0] fifo_rd_select_reg = 0;
+        reg fifo_rd_decerr_reg = 0;
+        reg fifo_rd_valid_reg = 0;
         wire fifo_rd_en;
         reg fifo_half_full_reg = 1'b0;
 
@@ -177,7 +182,13 @@ generate
                 fifo_decerr[fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= fifo_wr_decerr;
                 fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
             end
-            if (fifo_rd_en) begin
+
+            fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en;
+
+            if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin
+                fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
+                fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
+                fifo_rd_valid_reg <= 1'b1;
                 fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
             end
 
@@ -186,6 +197,7 @@ generate
             if (rst) begin
                 fifo_wr_ptr_reg <= 0;
                 fifo_rd_ptr_reg <= 0;
+                fifo_rd_valid_reg <= 1'b0;
             end
         end
 
@@ -258,9 +270,9 @@ generate
         assign m_rc_ready = !fifo_half_full_reg;
 
         // write response handling
-        wire [CL_M_COUNT-1:0] r_select = M_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]] : 0;
-        wire r_decerr = fifo_decerr[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
-        wire r_valid = !fifo_empty;
+        wire [CL_M_COUNT-1:0] r_select = M_COUNT > 1 ? fifo_rd_select_reg : 0;
+        wire r_decerr = fifo_rd_decerr_reg;
+        wire r_valid = fifo_rd_valid_reg;
 
         // read response mux
         wire [DATA_WIDTH-1:0]  m_axil_rdata_mux  = r_decerr ? {DATA_WIDTH{1'b0}} : int_m_axil_rdata[r_select*DATA_WIDTH +: DATA_WIDTH];
diff --git a/rtl/axil_crossbar_wr.v b/rtl/axil_crossbar_wr.v
index db08a7b..6fbbca2 100644
--- a/rtl/axil_crossbar_wr.v
+++ b/rtl/axil_crossbar_wr.v
@@ -173,9 +173,14 @@ generate
         reg [CL_M_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0];
         (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
         reg fifo_decerr[(2**FIFO_ADDR_WIDTH)-1:0];
+
         wire [CL_M_COUNT-1:0] fifo_wr_select;
         wire fifo_wr_decerr;
         wire fifo_wr_en;
+
+        reg [CL_M_COUNT-1:0] fifo_rd_select_reg = 0;
+        reg fifo_rd_decerr_reg = 0;
+        reg fifo_rd_valid_reg = 0;
         wire fifo_rd_en;
         reg fifo_half_full_reg = 1'b0;
 
@@ -196,7 +201,13 @@ generate
                 fifo_decerr[fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= fifo_wr_decerr;
                 fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
             end
-            if (fifo_rd_en) begin
+
+            fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en;
+
+            if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin
+                fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
+                fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
+                fifo_rd_valid_reg <= 1'b1;
                 fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
             end
 
@@ -205,6 +216,7 @@ generate
             if (rst) begin
                 fifo_wr_ptr_reg <= 0;
                 fifo_rd_ptr_reg <= 0;
+                fifo_rd_valid_reg <= 1'b0;
             end
         end
 
@@ -316,9 +328,9 @@ generate
         assign m_rc_ready = !fifo_half_full_reg;
 
         // write response handling
-        wire [CL_M_COUNT-1:0] b_select = M_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]] : 0;
-        wire b_decerr = fifo_decerr[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
-        wire b_valid = !fifo_empty;
+        wire [CL_M_COUNT-1:0] b_select = M_COUNT > 1 ? fifo_rd_select_reg : 0;
+        wire b_decerr = fifo_rd_decerr_reg;
+        wire b_valid = fifo_rd_valid_reg;
 
         // write response mux
         wire [1:0]  m_axil_bresp_mux  = b_decerr ? 2'b11 : int_m_axil_bresp[b_select*2 +: 2];