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https://github.com/alexforencich/verilog-axi.git
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Extract parameter values from cocotb.top
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@ -186,7 +186,7 @@ def cycle_pause():
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if cocotb.SIM_NAME:
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data_width = int(os.getenv("PARAM_S_DATA_WIDTH"))
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data_width = len(cocotb.top.s_axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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@ -186,7 +186,7 @@ def cycle_pause():
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if cocotb.SIM_NAME:
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data_width = int(os.getenv("PARAM_AXI_DATA_WIDTH"))
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data_width = len(cocotb.top.s_axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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@ -206,7 +206,7 @@ if cocotb.SIM_NAME:
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s_count = int(os.getenv("PARAM_S_COUNT"))
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m_count = int(os.getenv("PARAM_M_COUNT"))
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data_width = int(os.getenv("PARAM_DATA_WIDTH"))
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data_width = len(cocotb.top.s00_axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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@ -218,7 +218,7 @@ def cycle_pause():
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if cocotb.SIM_NAME:
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data_width = int(os.getenv("PARAM_DATA_WIDTH"))
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data_width = len(cocotb.top.s_axi_a_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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@ -187,7 +187,7 @@ def cycle_pause():
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if cocotb.SIM_NAME:
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data_width = int(os.getenv("PARAM_DATA_WIDTH"))
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data_width = len(cocotb.top.s_axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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@ -200,7 +200,7 @@ if cocotb.SIM_NAME:
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s_count = int(os.getenv("PARAM_S_COUNT"))
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m_count = int(os.getenv("PARAM_M_COUNT"))
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data_width = int(os.getenv("PARAM_DATA_WIDTH"))
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data_width = len(cocotb.top.s00_axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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@ -178,7 +178,7 @@ def cycle_pause():
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if cocotb.SIM_NAME:
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data_width = int(os.getenv("PARAM_DATA_WIDTH"))
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data_width = len(cocotb.top.s_axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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@ -186,7 +186,7 @@ def cycle_pause():
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if cocotb.SIM_NAME:
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data_width = int(os.getenv("PARAM_DATA_WIDTH"))
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data_width = len(cocotb.top.s_axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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