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Remove unnecessary wait state when output is ready
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@ -214,7 +214,7 @@ if (FIFO_DELAY) begin
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case (state_reg)
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STATE_IDLE: begin
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s_axi_arready_next = !m_axi_arvalid;
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s_axi_arready_next = !m_axi_arvalid || m_axi_arready;
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if (s_axi_arready && s_axi_arvalid) begin
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s_axi_arready_next = 1'b0;
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@ -229,7 +229,7 @@ if (FIFO_DELAY) begin
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case (state_reg)
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STATE_IDLE: begin
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s_axi_awready_next = !m_axi_awvalid;
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s_axi_awready_next = !m_axi_awvalid || m_axi_awready;
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hold_next = 1'b1;
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if (s_axi_awready && s_axi_awvalid) begin
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