FPGA/verilog-axi
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Check for disconnected ports

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This commit is contained in:
Alex Forencich 2018-08-11 23:09:00 -07:00
parent 0cb456e047
commit e29114fe04
1 changed files with 8 additions and 0 deletions
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8
tb/axi.py
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@ -251,6 +251,10 @@ class AXIMaster(object):
if not self.write_command_queue:
yield self.write_command_sync
if m_axi_awaddr is None:
print("Error: attempted write on read-only interface")
raise StopSimulation
addr, data, burst, size, lock, cache, prot, qos, region, user = self.write_command_queue.pop(0)
self.in_flight_operations += 1
@ -410,6 +414,10 @@ class AXIMaster(object):
if not self.read_command_queue:
yield self.read_command_sync
if m_axi_araddr is None:
print("Error: attempted read on write-only interface")
raise StopSimulation
addr, length, burst, size, lock, cache, prot, qos, region, user = self.read_command_queue.pop(0)
self.in_flight_operations += 1