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https://github.com/alexforencich/verilog-axi.git
synced 2025-01-14 06:42:55 +08:00
Use wlast instead of awlen to detect end of write burst
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c7d74b6425
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@ -260,13 +260,13 @@ if (FIFO_DELAY) begin
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if (s_axi_wready && s_axi_wvalid) begin
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count_next = count_reg + 1;
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if (count_next == 2**FIFO_ADDR_WIDTH) begin
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m_axi_awvalid_next = 1'b1;
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state_next = STATE_TRANSFER_OUT;
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end else if (count_reg == m_axi_awlen) begin
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if (s_axi_wlast) begin
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m_axi_awvalid_next = 1'b1;
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hold_next = 1'b1;
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state_next = STATE_IDLE;
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end else if (FIFO_ADDR_WIDTH < 8 && count_next == 2**FIFO_ADDR_WIDTH) begin
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m_axi_awvalid_next = 1'b1;
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state_next = STATE_TRANSFER_OUT;
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end else begin
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state_next = STATE_TRANSFER_IN;
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end
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@ -279,8 +279,7 @@ if (FIFO_DELAY) begin
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hold_next = 1'b0;
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if (s_axi_wready && s_axi_wvalid) begin
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count_next = count_reg + 1;
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if (count_reg == m_axi_awlen) begin
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if (s_axi_wlast) begin
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hold_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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