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Add AXI lite shared interconnect module and testbench

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Alex Forencich 2018-08-22 20:34:31 -07:00
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite interconnect
*/
module axil_interconnect #
(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter STRB_WIDTH = (DATA_WIDTH/8),
parameter S_COUNT = 4,
parameter M_COUNT = 4,
parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000},
parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24},
parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111},
parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111}
)
(
input wire clk,
input wire rst,
/*
* AXI lite slave interfaces
*/
input wire [S_COUNT*ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [S_COUNT*3-1:0] s_axil_awprot,
input wire [S_COUNT-1:0] s_axil_awvalid,
output wire [S_COUNT-1:0] s_axil_awready,
input wire [S_COUNT*DATA_WIDTH-1:0] s_axil_wdata,
input wire [S_COUNT*STRB_WIDTH-1:0] s_axil_wstrb,
input wire [S_COUNT-1:0] s_axil_wvalid,
output wire [S_COUNT-1:0] s_axil_wready,
output wire [S_COUNT*2-1:0] s_axil_bresp,
output wire [S_COUNT-1:0] s_axil_bvalid,
input wire [S_COUNT-1:0] s_axil_bready,
input wire [S_COUNT*ADDR_WIDTH-1:0] s_axil_araddr,
input wire [S_COUNT*3-1:0] s_axil_arprot,
input wire [S_COUNT-1:0] s_axil_arvalid,
output wire [S_COUNT-1:0] s_axil_arready,
output wire [S_COUNT*DATA_WIDTH-1:0] s_axil_rdata,
output wire [S_COUNT*2-1:0] s_axil_rresp,
output wire [S_COUNT-1:0] s_axil_rvalid,
input wire [S_COUNT-1:0] s_axil_rready,
/*
* AXI lite master interfaces
*/
output wire [M_COUNT*ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [M_COUNT*3-1:0] m_axil_awprot,
output wire [M_COUNT-1:0] m_axil_awvalid,
input wire [M_COUNT-1:0] m_axil_awready,
output wire [M_COUNT*DATA_WIDTH-1:0] m_axil_wdata,
output wire [M_COUNT*STRB_WIDTH-1:0] m_axil_wstrb,
output wire [M_COUNT-1:0] m_axil_wvalid,
input wire [M_COUNT-1:0] m_axil_wready,
input wire [M_COUNT*2-1:0] m_axil_bresp,
input wire [M_COUNT-1:0] m_axil_bvalid,
output wire [M_COUNT-1:0] m_axil_bready,
output wire [M_COUNT*ADDR_WIDTH-1:0] m_axil_araddr,
output wire [M_COUNT*3-1:0] m_axil_arprot,
output wire [M_COUNT-1:0] m_axil_arvalid,
input wire [M_COUNT-1:0] m_axil_arready,
input wire [M_COUNT*DATA_WIDTH-1:0] m_axil_rdata,
input wire [M_COUNT*2-1:0] m_axil_rresp,
input wire [M_COUNT-1:0] m_axil_rvalid,
output wire [M_COUNT-1:0] m_axil_rready
);
parameter CL_S_COUNT = $clog2(S_COUNT);
parameter CL_M_COUNT = $clog2(M_COUNT);
integer i, j;
// check configuration
initial begin
for (i = 0; i < M_COUNT; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 0 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
$error("Error: value out of range");
$finish;
end
end
end
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_DECODE = 3'd1,
STATE_WRITE = 3'd2,
STATE_WRITE_RESP = 3'd3,
STATE_WRITE_DROP = 3'd4,
STATE_READ = 3'd5,
STATE_WAIT_IDLE = 3'd6;
reg [2:0] state_reg = STATE_IDLE, state_next;
reg match;
reg [CL_M_COUNT-1:0] m_select_reg = 2'd0, m_select_next;
reg [ADDR_WIDTH-1:0] axil_addr_reg = {ADDR_WIDTH{1'b0}}, axil_addr_next;
reg axil_addr_valid_reg = 1'b0, axil_addr_valid_next;
reg [2:0] axil_prot_reg = 3'b000, axil_prot_next;
reg [DATA_WIDTH-1:0] axil_data_reg = {DATA_WIDTH{1'b0}}, axil_data_next;
reg [STRB_WIDTH-1:0] axil_wstrb_reg = {STRB_WIDTH{1'b0}}, axil_wstrb_next;
reg [1:0] axil_resp_reg = 2'b00, axil_resp_next;
reg [S_COUNT-1:0] s_axil_awready_reg = 0, s_axil_awready_next;
reg [S_COUNT-1:0] s_axil_wready_reg = 0, s_axil_wready_next;
reg [S_COUNT-1:0] s_axil_bvalid_reg = 0, s_axil_bvalid_next;
reg [S_COUNT-1:0] s_axil_arready_reg = 0, s_axil_arready_next;
reg [S_COUNT-1:0] s_axil_rvalid_reg = 0, s_axil_rvalid_next;
reg [M_COUNT-1:0] m_axil_awvalid_reg = 0, m_axil_awvalid_next;
reg [M_COUNT-1:0] m_axil_wvalid_reg = 0, m_axil_wvalid_next;
reg [M_COUNT-1:0] m_axil_bready_reg = 0, m_axil_bready_next;
reg [M_COUNT-1:0] m_axil_arvalid_reg = 0, m_axil_arvalid_next;
reg [M_COUNT-1:0] m_axil_rready_reg = 0, m_axil_rready_next;
assign s_axil_awready = s_axil_awready_reg;
assign s_axil_wready = s_axil_wready_reg;
assign s_axil_bresp = {S_COUNT{axil_resp_reg}};
assign s_axil_bvalid = s_axil_bvalid_reg;
assign s_axil_arready = s_axil_arready_reg;
assign s_axil_rdata = {S_COUNT{axil_data_reg}};
assign s_axil_rresp = {S_COUNT{axil_resp_reg}};
assign s_axil_rvalid = s_axil_rvalid_reg;
assign m_axil_awaddr = {M_COUNT{axil_addr_reg}};
assign m_axil_awprot = {M_COUNT{axil_prot_reg}};
assign m_axil_awvalid = m_axil_awvalid_reg;
assign m_axil_wdata = {M_COUNT{axil_data_reg}};
assign m_axil_wstrb = {M_COUNT{axil_wstrb_reg}};
assign m_axil_wvalid = m_axil_wvalid_reg;
assign m_axil_bready = m_axil_bready_reg;
assign m_axil_araddr = {M_COUNT{axil_addr_reg}};
assign m_axil_arprot = {M_COUNT{axil_prot_reg}};
assign m_axil_arvalid = m_axil_arvalid_reg;
assign m_axil_rready = m_axil_rready_reg;
// slave side mux
wire [ADDR_WIDTH-1:0] current_s_axil_awaddr = s_axil_awaddr[s_select*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_s_axil_awprot = s_axil_awprot[s_select*3 +: 3];
wire current_s_axil_awvalid = s_axil_awvalid[s_select];
wire current_s_axil_awready = s_axil_awready[s_select];
wire [DATA_WIDTH-1:0] current_s_axil_wdata = s_axil_wdata[s_select*DATA_WIDTH +: DATA_WIDTH];
wire [STRB_WIDTH-1:0] current_s_axil_wstrb = s_axil_wstrb[s_select*STRB_WIDTH +: STRB_WIDTH];
wire current_s_axil_wvalid = s_axil_wvalid[s_select];
wire current_s_axil_wready = s_axil_wready[s_select];
wire [1:0] current_s_axil_bresp = s_axil_bresp[s_select*2 +: 2];
wire current_s_axil_bvalid = s_axil_bvalid[s_select];
wire current_s_axil_bready = s_axil_bready[s_select];
wire [ADDR_WIDTH-1:0] current_s_axil_araddr = s_axil_araddr[s_select*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_s_axil_arprot = s_axil_arprot[s_select*3 +: 3];
wire current_s_axil_arvalid = s_axil_arvalid[s_select];
wire current_s_axil_arready = s_axil_arready[s_select];
wire [DATA_WIDTH-1:0] current_s_axil_rdata = s_axil_rdata[s_select*DATA_WIDTH +: DATA_WIDTH];
wire [1:0] current_s_axil_rresp = s_axil_rresp[s_select*2 +: 2];
wire current_s_axil_rvalid = s_axil_rvalid[s_select];
wire current_s_axil_rready = s_axil_rready[s_select];
// master side mux
wire [ADDR_WIDTH-1:0] current_m_axil_awaddr = m_axil_awaddr[m_select_reg*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_m_axil_awprot = m_axil_awprot[m_select_reg*3 +: 3];
wire current_m_axil_awvalid = m_axil_awvalid[m_select_reg];
wire current_m_axil_awready = m_axil_awready[m_select_reg];
wire [DATA_WIDTH-1:0] current_m_axil_wdata = m_axil_wdata[m_select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [STRB_WIDTH-1:0] current_m_axil_wstrb = m_axil_wstrb[m_select_reg*STRB_WIDTH +: STRB_WIDTH];
wire current_m_axil_wvalid = m_axil_wvalid[m_select_reg];
wire current_m_axil_wready = m_axil_wready[m_select_reg];
wire [1:0] current_m_axil_bresp = m_axil_bresp[m_select_reg*2 +: 2];
wire current_m_axil_bvalid = m_axil_bvalid[m_select_reg];
wire current_m_axil_bready = m_axil_bready[m_select_reg];
wire [ADDR_WIDTH-1:0] current_m_axil_araddr = m_axil_araddr[m_select_reg*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_m_axil_arprot = m_axil_arprot[m_select_reg*3 +: 3];
wire current_m_axil_arvalid = m_axil_arvalid[m_select_reg];
wire current_m_axil_arready = m_axil_arready[m_select_reg];
wire [DATA_WIDTH-1:0] current_m_axil_rdata = m_axil_rdata[m_select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [1:0] current_m_axil_rresp = m_axil_rresp[m_select_reg*2 +: 2];
wire current_m_axil_rvalid = m_axil_rvalid[m_select_reg];
wire current_m_axil_rready = m_axil_rready[m_select_reg];
// arbiter instance
wire [S_COUNT*2-1:0] request;
wire [S_COUNT*2-1:0] acknowledge;
wire [S_COUNT*2-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT:0] grant_encoded;
wire read = grant_encoded[0];
wire [CL_S_COUNT-1:0] s_select = grant_encoded[CL_S_COUNT:1];
arbiter #(
.PORTS(S_COUNT*2),
.TYPE("ROUND_ROBIN"),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY("HIGH")
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
genvar n;
// request generation
generate
for (n = 0; n < S_COUNT; n = n + 1) begin
assign request[2*n] = s_axil_awvalid[n] && (!s_axil_bvalid[n] || s_axil_bready[n]) && (!s_axil_rvalid[n] || s_axil_rready[n]);
assign request[2*n+1] = s_axil_arvalid[n] && (!s_axil_bvalid[n] || s_axil_bready[n]) && (!s_axil_rvalid[n] || s_axil_rready[n]);
end
endgenerate
// acknowledge generation
generate
for (n = 0; n < S_COUNT; n = n + 1) begin
assign acknowledge[2*n] = grant[2*n] && s_axil_bvalid[n] && s_axil_bready[n];
assign acknowledge[2*n+1] = grant[2*n+1] && s_axil_rvalid[n] && s_axil_rready[n];
end
endgenerate
always @* begin
state_next = STATE_IDLE;
match = 1'b0;
m_select_next = m_select_reg;
axil_addr_next = axil_addr_reg;
axil_addr_valid_next = axil_addr_valid_reg;
axil_prot_next = axil_prot_reg;
axil_data_next = axil_data_reg;
axil_wstrb_next = axil_wstrb_reg;
axil_resp_next = axil_resp_reg;
s_axil_awready_next = 0;
s_axil_wready_next = 0;
s_axil_bvalid_next = s_axil_bvalid_reg & ~s_axil_bready;
s_axil_arready_next = 0;
s_axil_rvalid_next = s_axil_rvalid_reg & ~s_axil_rready;
m_axil_awvalid_next = m_axil_awvalid_reg & ~m_axil_awready;
m_axil_wvalid_next = m_axil_wvalid_reg & ~m_axil_wready;
m_axil_bready_next = 0;
m_axil_arvalid_next = m_axil_arvalid_reg & ~m_axil_arready;
m_axil_rready_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state; wait for arbitration
if (grant_valid) begin
axil_addr_valid_next = 1'b1;
if (read) begin
// reading
axil_addr_next = current_s_axil_araddr;
axil_prot_next = current_s_axil_arprot;
s_axil_arready_next[s_select] = 1'b1;
end else begin
// writing
axil_addr_next = current_s_axil_awaddr;
axil_prot_next = current_s_axil_awprot;
s_axil_awready_next[s_select] = 1'b1;
end
state_next = STATE_DECODE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DECODE: begin
// decode state; determine master interface
match = 1'b0;
for (i = 0; i < M_COUNT; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (read ? M_CONNECT_READ[i][s_select] : M_CONNECT_WRITE[i][s_select]) && (axil_addr_reg >> M_ADDR_WIDTH[i*32 +: 32]) == (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[i*32 +: 32])) begin
m_select_next = i;
match = 1'b1;
end
end
if (match) begin
if (read) begin
// reading
m_axil_rready_next[m_select_reg] = 1'b1;
state_next = STATE_READ;
end else begin
// writing
s_axil_wready_next[s_select] = 1'b1;
state_next = STATE_WRITE;
end
end else begin
// no match; return decode error
axil_data_next = {DATA_WIDTH{1'b0}};
axil_resp_next = 2'b11;
if (read) begin
// reading
s_axil_rvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
// writing
s_axil_wready_next[s_select] = 1'b1;
state_next = STATE_WRITE_DROP;
end
end
end
STATE_WRITE: begin
// write state; store and forward write data
s_axil_wready_next[s_select] = 1'b1;
if (axil_addr_valid_reg) begin
m_axil_awvalid_next[m_select_reg] = 1'b1;
end
axil_addr_valid_next = 1'b0;
if (current_s_axil_wready && current_s_axil_wvalid) begin
s_axil_wready_next[s_select] = 1'b0;
axil_data_next = current_s_axil_wdata;
axil_wstrb_next = current_s_axil_wstrb;
m_axil_wvalid_next[m_select_reg] = 1'b1;
m_axil_bready_next[m_select_reg] = 1'b1;
state_next = STATE_WRITE_RESP;
end else begin
state_next = STATE_WRITE;
end
end
STATE_WRITE_RESP: begin
// write response state; store and forward write response
m_axil_bready_next[m_select_reg] = 1'b1;
if (current_m_axil_bready && current_m_axil_bvalid) begin
m_axil_bready_next[m_select_reg] = 1'b0;
axil_resp_next = current_m_axil_bresp;
s_axil_bvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
state_next = STATE_WRITE_RESP;
end
end
STATE_WRITE_DROP: begin
// write drop state; drop write data
s_axil_wready_next[s_select] = 1'b1;
axil_addr_valid_next = 1'b0;
if (current_s_axil_wready && current_s_axil_wvalid) begin
s_axil_wready_next[s_select] = 1'b0;
s_axil_bvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
state_next = STATE_WRITE_DROP;
end
end
STATE_READ: begin
// read state; store and forward read response
m_axil_rready_next[m_select_reg] = 1'b1;
if (axil_addr_valid_reg) begin
m_axil_arvalid_next[m_select_reg] = 1'b1;
end
axil_addr_valid_next = 1'b0;
if (current_m_axil_rready && current_m_axil_rvalid) begin
m_axil_rready_next[m_select_reg] = 1'b0;
axil_data_next = current_m_axil_rdata;
axil_resp_next = current_m_axil_rresp;
s_axil_rvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
state_next = STATE_READ;
end
end
STATE_WAIT_IDLE: begin
// wait for idle state; wait untl grant valid is deasserted
if (current_s_axil_wready) begin
// dump any write data
s_axil_wready_next[s_select] = !current_s_axil_wvalid;
end
if (!grant_valid || acknowledge) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_IDLE;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axil_awready_reg <= 0;
s_axil_wready_reg <= 0;
s_axil_bvalid_reg <= 0;
s_axil_arready_reg <= 0;
s_axil_rvalid_reg <= 0;
m_axil_awvalid_reg <= 0;
m_axil_wvalid_reg <= 0;
m_axil_bready_reg <= 0;
m_axil_arvalid_reg <= 0;
m_axil_rready_reg <= 0;
end else begin
state_reg <= state_next;
s_axil_awready_reg <= s_axil_awready_next;
s_axil_wready_reg <= s_axil_wready_next;
s_axil_bvalid_reg <= s_axil_bvalid_next;
s_axil_arready_reg <= s_axil_arready_next;
s_axil_rvalid_reg <= s_axil_rvalid_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
end
m_select_reg <= m_select_next;
axil_addr_reg <= axil_addr_next;
axil_addr_valid_reg <= axil_addr_valid_next;
axil_prot_reg <= axil_prot_next;
axil_data_reg <= axil_data_next;
axil_wstrb_reg <= axil_wstrb_next;
axil_resp_reg <= axil_resp_next;
end
endmodule

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tb/test_axil_interconnect_4x4.py Executable file
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#!/usr/bin/env python
"""
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
import axil
module = 'axil_interconnect'
testbench = 'test_%s_4x4' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/arbiter.v")
srcs.append("../rtl/priority_encoder.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
STRB_WIDTH = (DATA_WIDTH/8)
S_COUNT = 4
M_COUNT = 4
M_BASE_ADDR = [0x00000000, 0x01000000, 0x02000000, 0x03000000]
M_ADDR_WIDTH = [24, 24, 24, 24]
M_CONNECT_READ = [0b1111, 0b1111, 0b1111, 0b1111]
M_CONNECT_WRITE = [0b1111, 0b1111, 0b1111, 0b1111]
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axil_awaddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
s_axil_awprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axil_awvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_wdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
s_axil_wstrb_list = [Signal(intbv(0)[STRB_WIDTH:]) for i in range(S_COUNT)]
s_axil_wvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_bready_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_araddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
s_axil_arprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axil_arvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_rready_list = [Signal(bool(0)) for i in range(S_COUNT)]
m_axil_awready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_wready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_bresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
m_axil_bvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_arready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_rdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(M_COUNT)]
m_axil_rresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
m_axil_rvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
s_axil_awaddr = ConcatSignal(*reversed(s_axil_awaddr_list))
s_axil_awprot = ConcatSignal(*reversed(s_axil_awprot_list))
s_axil_awvalid = ConcatSignal(*reversed(s_axil_awvalid_list))
s_axil_wdata = ConcatSignal(*reversed(s_axil_wdata_list))
s_axil_wstrb = ConcatSignal(*reversed(s_axil_wstrb_list))
s_axil_wvalid = ConcatSignal(*reversed(s_axil_wvalid_list))
s_axil_bready = ConcatSignal(*reversed(s_axil_bready_list))
s_axil_araddr = ConcatSignal(*reversed(s_axil_araddr_list))
s_axil_arprot = ConcatSignal(*reversed(s_axil_arprot_list))
s_axil_arvalid = ConcatSignal(*reversed(s_axil_arvalid_list))
s_axil_rready = ConcatSignal(*reversed(s_axil_rready_list))
m_axil_awready = ConcatSignal(*reversed(m_axil_awready_list))
m_axil_wready = ConcatSignal(*reversed(m_axil_wready_list))
m_axil_bresp = ConcatSignal(*reversed(m_axil_bresp_list))
m_axil_bvalid = ConcatSignal(*reversed(m_axil_bvalid_list))
m_axil_arready = ConcatSignal(*reversed(m_axil_arready_list))
m_axil_rdata = ConcatSignal(*reversed(m_axil_rdata_list))
m_axil_rresp = ConcatSignal(*reversed(m_axil_rresp_list))
m_axil_rvalid = ConcatSignal(*reversed(m_axil_rvalid_list))
# Outputs
s_axil_awready = Signal(intbv(0)[S_COUNT:])
s_axil_wready = Signal(intbv(0)[S_COUNT:])
s_axil_bresp = Signal(intbv(0)[S_COUNT*2:])
s_axil_bvalid = Signal(intbv(0)[S_COUNT:])
s_axil_arready = Signal(intbv(0)[S_COUNT:])
s_axil_rdata = Signal(intbv(0)[S_COUNT*DATA_WIDTH:])
s_axil_rresp = Signal(intbv(0)[S_COUNT*2:])
s_axil_rvalid = Signal(intbv(0)[S_COUNT:])
m_axil_awaddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:])
m_axil_awprot = Signal(intbv(0)[M_COUNT*3:])
m_axil_awvalid = Signal(intbv(0)[M_COUNT:])
m_axil_wdata = Signal(intbv(0)[M_COUNT*DATA_WIDTH:])
m_axil_wstrb = Signal(intbv(0)[M_COUNT*STRB_WIDTH:])
m_axil_wvalid = Signal(intbv(0)[M_COUNT:])
m_axil_bready = Signal(intbv(0)[M_COUNT:])
m_axil_araddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:])
m_axil_arprot = Signal(intbv(0)[M_COUNT*3:])
m_axil_arvalid = Signal(intbv(0)[M_COUNT:])
m_axil_rready = Signal(intbv(0)[M_COUNT:])
s_axil_awready_list = [s_axil_awready(i) for i in range(S_COUNT)]
s_axil_wready_list = [s_axil_wready(i) for i in range(S_COUNT)]
s_axil_bresp_list = [s_axil_bresp((i+1)*2, i*2) for i in range(S_COUNT)]
s_axil_bvalid_list = [s_axil_bvalid(i) for i in range(S_COUNT)]
s_axil_arready_list = [s_axil_arready(i) for i in range(S_COUNT)]
s_axil_rdata_list = [s_axil_rdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(S_COUNT)]
s_axil_rresp_list = [s_axil_rresp((i+1)*2, i*2) for i in range(S_COUNT)]
s_axil_rvalid_list = [s_axil_rvalid(i) for i in range(S_COUNT)]
m_axil_awaddr_list = [m_axil_awaddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)]
m_axil_awprot_list = [m_axil_awprot((i+1)*3, i*3) for i in range(M_COUNT)]
m_axil_awvalid_list = [m_axil_awvalid(i) for i in range(M_COUNT)]
m_axil_wdata_list = [m_axil_wdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(M_COUNT)]
m_axil_wstrb_list = [m_axil_wstrb((i+1)*STRB_WIDTH, i*STRB_WIDTH) for i in range(M_COUNT)]
m_axil_wvalid_list = [m_axil_wvalid(i) for i in range(M_COUNT)]
m_axil_bready_list = [m_axil_bready(i) for i in range(M_COUNT)]
m_axil_araddr_list = [m_axil_araddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)]
m_axil_arprot_list = [m_axil_arprot((i+1)*3, i*3) for i in range(M_COUNT)]
m_axil_arvalid_list = [m_axil_arvalid(i) for i in range(M_COUNT)]
m_axil_rready_list = [m_axil_rready(i) for i in range(M_COUNT)]
# AXI4-Lite masters
axil_master_inst_list = []
axil_master_pause_list = []
axil_master_logic = []
for k in range(S_COUNT):
m = axil.AXILiteMaster()
p = Signal(bool(False))
axil_master_inst_list.append(m)
axil_master_pause_list.append(p)
axil_master_logic.append(m.create_logic(
clk,
rst,
m_axil_awaddr=s_axil_awaddr_list[k],
m_axil_awprot=s_axil_awprot_list[k],
m_axil_awvalid=s_axil_awvalid_list[k],
m_axil_awready=s_axil_awready_list[k],
m_axil_wdata=s_axil_wdata_list[k],
m_axil_wstrb=s_axil_wstrb_list[k],
m_axil_wvalid=s_axil_wvalid_list[k],
m_axil_wready=s_axil_wready_list[k],
m_axil_bresp=s_axil_bresp_list[k],
m_axil_bvalid=s_axil_bvalid_list[k],
m_axil_bready=s_axil_bready_list[k],
m_axil_araddr=s_axil_araddr_list[k],
m_axil_arprot=s_axil_arprot_list[k],
m_axil_arvalid=s_axil_arvalid_list[k],
m_axil_arready=s_axil_arready_list[k],
m_axil_rdata=s_axil_rdata_list[k],
m_axil_rresp=s_axil_rresp_list[k],
m_axil_rvalid=s_axil_rvalid_list[k],
m_axil_rready=s_axil_rready_list[k],
pause=p,
name='master_%d' % k
))
# AXI4-Lite RAM models
axil_ram_inst_list = []
axil_ram_pause_list = []
axil_ram_logic = []
for k in range(M_COUNT):
r = axil.AXILiteRam(2**16)
p = Signal(bool(False))
axil_ram_inst_list.append(r)
axil_ram_pause_list.append(p)
axil_ram_logic.append(r.create_port(
clk,
s_axil_awaddr=m_axil_awaddr_list[k],
s_axil_awprot=m_axil_awprot_list[k],
s_axil_awvalid=m_axil_awvalid_list[k],
s_axil_awready=m_axil_awready_list[k],
s_axil_wdata=m_axil_wdata_list[k],
s_axil_wstrb=m_axil_wstrb_list[k],
s_axil_wvalid=m_axil_wvalid_list[k],
s_axil_wready=m_axil_wready_list[k],
s_axil_bresp=m_axil_bresp_list[k],
s_axil_bvalid=m_axil_bvalid_list[k],
s_axil_bready=m_axil_bready_list[k],
s_axil_araddr=m_axil_araddr_list[k],
s_axil_arprot=m_axil_arprot_list[k],
s_axil_arvalid=m_axil_arvalid_list[k],
s_axil_arready=m_axil_arready_list[k],
s_axil_rdata=m_axil_rdata_list[k],
s_axil_rresp=m_axil_rresp_list[k],
s_axil_rvalid=m_axil_rvalid_list[k],
s_axil_rready=m_axil_rready_list[k],
pause=p,
latency=1,
name='ram_%d' % k
))
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axil_awaddr=s_axil_awaddr,
s_axil_awprot=s_axil_awprot,
s_axil_awvalid=s_axil_awvalid,
s_axil_awready=s_axil_awready,
s_axil_wdata=s_axil_wdata,
s_axil_wstrb=s_axil_wstrb,
s_axil_wvalid=s_axil_wvalid,
s_axil_wready=s_axil_wready,
s_axil_bresp=s_axil_bresp,
s_axil_bvalid=s_axil_bvalid,
s_axil_bready=s_axil_bready,
s_axil_araddr=s_axil_araddr,
s_axil_arprot=s_axil_arprot,
s_axil_arvalid=s_axil_arvalid,
s_axil_arready=s_axil_arready,
s_axil_rdata=s_axil_rdata,
s_axil_rresp=s_axil_rresp,
s_axil_rvalid=s_axil_rvalid,
s_axil_rready=s_axil_rready,
m_axil_awaddr=m_axil_awaddr,
m_axil_awprot=m_axil_awprot,
m_axil_awvalid=m_axil_awvalid,
m_axil_awready=m_axil_awready,
m_axil_wdata=m_axil_wdata,
m_axil_wstrb=m_axil_wstrb,
m_axil_wvalid=m_axil_wvalid,
m_axil_wready=m_axil_wready,
m_axil_bresp=m_axil_bresp,
m_axil_bvalid=m_axil_bvalid,
m_axil_bready=m_axil_bready,
m_axil_araddr=m_axil_araddr,
m_axil_arprot=m_axil_arprot,
m_axil_arvalid=m_axil_arvalid,
m_axil_arready=m_axil_arready,
m_axil_rdata=m_axil_rdata,
m_axil_rresp=m_axil_rresp,
m_axil_rvalid=m_axil_rvalid,
m_axil_rready=m_axil_rready
)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]):
yield clk.posedge
def wait_pause_master():
while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]):
for k in range(S_COUNT):
axil_master_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
axil_master_pause_list[k].next = False
yield clk.posedge
def wait_pause_slave():
while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]):
for k in range(M_COUNT):
axil_ram_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(M_COUNT):
axil_ram_pause_list[k].next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write")
current_test.next = 1
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_master_inst_list[0].init_write(addr, test_data)
yield axil_master_inst_list[0].wait()
yield clk.posedge
data = axil_ram_inst_list[0].read_mem(addr&0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axil_ram_inst_list[0].read_mem(addr, len(test_data)) == test_data
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_ram_inst_list[0].write_mem(addr, test_data)
axil_master_inst_list[0].init_read(addr, len(test_data))
yield axil_master_inst_list[0].wait()
yield clk.posedge
data = axil_master_inst_list[0].get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 3: one to many")
current_test.next = 3
addr = 4
test_data = b'\x11\x22\x33\x44'
for k in range(S_COUNT):
axil_master_inst_list[0].init_write(addr+M_BASE_ADDR[k], test_data)
yield axil_master_inst_list[0].wait()
yield clk.posedge
for k in range(S_COUNT):
data = axil_ram_inst_list[k].read_mem(addr&0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
for k in range(S_COUNT):
assert axil_ram_inst_list[k].read_mem(addr, len(test_data)) == test_data
for k in range(S_COUNT):
axil_master_inst_list[0].init_read(addr+M_BASE_ADDR[k], len(test_data))
yield axil_master_inst_list[0].wait()
yield clk.posedge
for k in range(S_COUNT):
data = axil_master_inst_list[0].get_read_data()
assert data[0] == addr+M_BASE_ADDR[k]
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 4: many to one")
current_test.next = 4
for k in range(M_COUNT):
axil_master_inst_list[k].init_write(k*4, bytearray([(k+1)*17]*4))
for k in range(M_COUNT):
yield axil_master_inst_list[k].wait()
yield clk.posedge
data = axil_ram_inst_list[0].read_mem(addr&0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
for k in range(M_COUNT):
assert axil_ram_inst_list[0].read_mem(k*4, 4) == bytearray([(k+1)*17]*4)
for k in range(M_COUNT):
axil_master_inst_list[k].init_read(k*4, 4)
for k in range(M_COUNT):
yield axil_master_inst_list[k].wait()
yield clk.posedge
for k in range(M_COUNT):
data = axil_master_inst_list[k].get_read_data()
assert data[0] == k*4
assert data[1] == bytearray([(k+1)*17]*4)
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_ram_inst_list[0].write_mem(256*(16*offset+length), b'\xAA'*32)
axil_master_inst_list[0].init_write(addr, test_data)
yield wait()
yield clk.posedge
data = axil_ram_inst_list[0].read_mem(256*(16*offset+length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axil_ram_inst_list[0].read_mem(addr, length) == test_data
assert axil_ram_inst_list[0].read_mem(addr-1, 1) == b'\xAA'
assert axil_ram_inst_list[0].read_mem(addr+length, 1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_master_inst_list[0].init_read(addr, length)
yield wait()
yield clk.posedge
data = axil_master_inst_list[0].get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 7: concurrent operations")
current_test.next = 7
for count in [1, 2, 4, 8]:
for stride in [2, 3, 5, 7]:
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("count %d, stride %d"% (count, stride))
for k in range(S_COUNT):
for l in range(count):
ram = ((k*61+l)*stride)%M_COUNT
offset = k*256+l*4
axil_ram_inst_list[ram].write_mem(offset, b'\xAA'*4)
axil_master_inst_list[k].init_write(M_BASE_ADDR[ram]+offset, bytearray([0xaa, k, l, 0xaa]))
ram = ((k*61+l+67)*stride)%M_COUNT
offset = k*256+l*4
axil_ram_inst_list[ram].write_mem(offset+0x8000, bytearray([0xaa, k, l, 0xaa]))
axil_master_inst_list[k].init_read(M_BASE_ADDR[ram]+offset+0x8000, 4)
yield wait()
yield clk.posedge
for k in range(S_COUNT):
for l in range(count):
ram = ((k*61+l)*stride)%M_COUNT
offset = k*256+l*4
axil_ram_inst_list[ram].read_mem(offset, 4) == bytearray([0xaa, k, l, 0xaa])
ram = ((k*61+l+67)*stride)%M_COUNT
offset = k*256+l*4
data = axil_master_inst_list[k].get_read_data()
assert data[0] == M_BASE_ADDR[ram]+offset+0x8000
assert data[1] == bytearray([0xaa, k, l, 0xaa])
yield delay(100)
raise StopSimulation
return instances()
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axil_interconnect
*/
module test_axil_interconnect_4x4;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter STRB_WIDTH = (DATA_WIDTH/8);
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000};
parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24};
parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111};
parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111};
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*ADDR_WIDTH-1:0] s_axil_awaddr = 0;
reg [S_COUNT*3-1:0] s_axil_awprot = 0;
reg [S_COUNT-1:0] s_axil_awvalid = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axil_wdata = 0;
reg [S_COUNT*STRB_WIDTH-1:0] s_axil_wstrb = 0;
reg [S_COUNT-1:0] s_axil_wvalid = 0;
reg [S_COUNT-1:0] s_axil_bready = 0;
reg [S_COUNT*ADDR_WIDTH-1:0] s_axil_araddr = 0;
reg [S_COUNT*3-1:0] s_axil_arprot = 0;
reg [S_COUNT-1:0] s_axil_arvalid = 0;
reg [S_COUNT-1:0] s_axil_rready = 0;
reg [M_COUNT-1:0] m_axil_awready = 0;
reg [M_COUNT-1:0] m_axil_wready = 0;
reg [M_COUNT*2-1:0] m_axil_bresp = 0;
reg [M_COUNT-1:0] m_axil_bvalid = 0;
reg [M_COUNT-1:0] m_axil_arready = 0;
reg [M_COUNT*DATA_WIDTH-1:0] m_axil_rdata = 0;
reg [M_COUNT*2-1:0] m_axil_rresp = 0;
reg [M_COUNT-1:0] m_axil_rvalid = 0;
// Outputs
wire [S_COUNT-1:0] s_axil_awready;
wire [S_COUNT-1:0] s_axil_wready;
wire [S_COUNT*2-1:0] s_axil_bresp;
wire [S_COUNT-1:0] s_axil_bvalid;
wire [S_COUNT-1:0] s_axil_arready;
wire [S_COUNT*DATA_WIDTH-1:0] s_axil_rdata;
wire [S_COUNT*2-1:0] s_axil_rresp;
wire [S_COUNT-1:0] s_axil_rvalid;
wire [M_COUNT*ADDR_WIDTH-1:0] m_axil_awaddr;
wire [M_COUNT*3-1:0] m_axil_awprot;
wire [M_COUNT-1:0] m_axil_awvalid;
wire [M_COUNT*DATA_WIDTH-1:0] m_axil_wdata;
wire [M_COUNT*STRB_WIDTH-1:0] m_axil_wstrb;
wire [M_COUNT-1:0] m_axil_wvalid;
wire [M_COUNT-1:0] m_axil_bready;
wire [M_COUNT*ADDR_WIDTH-1:0] m_axil_araddr;
wire [M_COUNT*3-1:0] m_axil_arprot;
wire [M_COUNT-1:0] m_axil_arvalid;
wire [M_COUNT-1:0] m_axil_rready;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axil_awaddr,
s_axil_awprot,
s_axil_awvalid,
s_axil_wdata,
s_axil_wstrb,
s_axil_wvalid,
s_axil_bready,
s_axil_araddr,
s_axil_arprot,
s_axil_arvalid,
s_axil_rready,
m_axil_awready,
m_axil_wready,
m_axil_bresp,
m_axil_bvalid,
m_axil_arready,
m_axil_rdata,
m_axil_rresp,
m_axil_rvalid
);
$to_myhdl(
s_axil_awready,
s_axil_wready,
s_axil_bresp,
s_axil_bvalid,
s_axil_arready,
s_axil_rdata,
s_axil_rresp,
s_axil_rvalid,
m_axil_awaddr,
m_axil_awprot,
m_axil_awvalid,
m_axil_wdata,
m_axil_wstrb,
m_axil_wvalid,
m_axil_bready,
m_axil_araddr,
m_axil_arprot,
m_axil_arvalid,
m_axil_rready
);
// dump file
$dumpfile("test_axil_interconnect_4x4.lxt");
$dumpvars(0, test_axil_interconnect_4x4);
end
axil_interconnect #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.S_COUNT(S_COUNT),
.M_COUNT(M_COUNT),
.M_BASE_ADDR(M_BASE_ADDR),
.M_ADDR_WIDTH(M_ADDR_WIDTH),
.M_CONNECT_READ(M_CONNECT_READ),
.M_CONNECT_WRITE(M_CONNECT_WRITE)
)
UUT (
.clk(clk),
.rst(rst),
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
.s_axil_wstrb(s_axil_wstrb),
.s_axil_wvalid(s_axil_wvalid),
.s_axil_wready(s_axil_wready),
.s_axil_bresp(s_axil_bresp),
.s_axil_bvalid(s_axil_bvalid),
.s_axil_bready(s_axil_bready),
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready),
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready),
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready)
);
endmodule