FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-14 06:42:55 +08:00
Code Issues Projects Releases Wiki Activity

Remove deprecated assigments

Browse Source
This commit is contained in:
Alex Forencich 2021-11-15 14:31:28 -08:00
parent 078bbc8f07
commit fbb507be82
20 changed files with 63 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tb/axi_adapter/test_axi_adapter.py
View File

@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
tb/axi_axil_adapter/test_axi_axil_adapter.py
View File

@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

6
tb/axi_cdma/test_axi_cdma.py
View File

@ -80,10 +80,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -103,7 +103,7 @@ async def run_test(dut, data_in=None, idle_inserter=None, backpressure_inserter=
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.enable <= 1
dut.enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for read_offset in list(range(8, 8+byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

4
tb/axi_crossbar/test_axi_crossbar.py
View File

@ -84,10 +84,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

8
tb/axi_dma/test_axi_dma.py
View File

@ -95,10 +95,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -118,7 +118,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.write_enable <= 1
dut.write_enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
@ -174,7 +174,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.read_enable <= 1
dut.read_enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

6
tb/axi_dma_rd/test_axi_dma_rd.py
View File

@ -82,10 +82,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -105,7 +105,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.enable <= 1
dut.enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

6
tb/axi_dma_wr/test_axi_dma_wr.py
View File

@ -83,10 +83,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -106,7 +106,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.enable <= 1
dut.enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

8
tb/axi_dp_ram/test_axi_dp_ram.py
View File

@ -71,13 +71,13 @@ class TB(object):
self.dut.b_rst.setimmediatevalue(0)
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 1
self.dut.b_rst <= 1
self.dut.a_rst.value = 1
self.dut.b_rst.value = 1
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 0
self.dut.a_rst.value = 0
await RisingEdge(self.dut.b_clk)
self.dut.b_rst <= 0
self.dut.b_rst.value = 0
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)

4
tb/axi_fifo/test_axi_fifo.py
View File

@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
tb/axi_interconnect/test_axi_interconnect.py
View File

@ -78,10 +78,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
tb/axi_ram/test_axi_ram.py
View File

@ -64,10 +64,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
tb/axi_register/test_axi_register.py
View File

@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
tb/axil_adapter/test_axil_adapter.py
View File

@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

8
tb/axil_cdc/test_axil_cdc.py
View File

@ -72,13 +72,13 @@ class TB(object):
self.dut.m_rst.setimmediatevalue(0)
await RisingEdge(self.dut.s_clk)
await RisingEdge(self.dut.s_clk)
self.dut.s_rst <= 1
self.dut.m_rst <= 1
self.dut.s_rst.value = 1
self.dut.m_rst.value = 1
await RisingEdge(self.dut.s_clk)
await RisingEdge(self.dut.s_clk)
self.dut.s_rst <= 0
self.dut.s_rst.value = 0
await RisingEdge(self.dut.m_clk)
self.dut.m_rst <= 0
self.dut.m_rst.value = 0
await RisingEdge(self.dut.s_clk)
await RisingEdge(self.dut.s_clk)

4
tb/axil_crossbar/test_axil_crossbar.py
View File

@ -78,10 +78,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

8
tb/axil_dp_ram/test_axil_dp_ram.py
View File

@ -71,13 +71,13 @@ class TB(object):
self.dut.b_rst.setimmediatevalue(0)
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 1
self.dut.b_rst <= 1
self.dut.a_rst.value = 1
self.dut.b_rst.value = 1
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 0
self.dut.a_rst.value = 0
await RisingEdge(self.dut.b_clk)
self.dut.b_rst <= 0
self.dut.b_rst.value = 0
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)

4
tb/axil_interconnect/test_axil_interconnect.py
View File

@ -78,10 +78,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
tb/axil_ram/test_axil_ram.py
View File

@ -64,10 +64,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

28
tb/axil_reg_if/test_axil_reg_if.py
View File

@ -76,10 +76,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -87,15 +87,15 @@ class TB(object):
byte_lanes = len(self.dut.reg_wr_strb)
while True:
self.dut.reg_rd_data <= 0
self.dut.reg_rd_wait <= 0
self.dut.reg_rd_ack <= 0
self.dut.reg_rd_data.value = 0
self.dut.reg_rd_wait.value = 0
self.dut.reg_rd_ack.value = 0
await RisingEdge(self.dut.clk)
addr = (self.dut.reg_rd_addr.value.integer // byte_lanes) * byte_lanes
if self.dut.reg_rd_en.value.integer and addr < len(self.mem):
self.dut.reg_rd_wait <= 1
self.dut.reg_rd_wait.value = 1
for k in range(10):
await RisingEdge(self.dut.clk)
@ -104,17 +104,17 @@ class TB(object):
data = self.mem.read(byte_lanes)
self.dut.reg_rd_data <= int.from_bytes(data, 'little')
self.dut.reg_rd_wait <= 0
self.dut.reg_rd_ack <= 1
self.dut.reg_rd_data.value = int.from_bytes(data, 'little')
self.dut.reg_rd_wait.value = 0
self.dut.reg_rd_ack.value = 1
await RisingEdge(self.dut.clk)
async def run_reg_write(self):
byte_lanes = len(self.dut.reg_wr_strb)
while True:
self.dut.reg_wr_wait <= 0
self.dut.reg_wr_ack <= 0
self.dut.reg_wr_wait.value = 0
self.dut.reg_wr_ack.value = 0
await RisingEdge(self.dut.clk)
addr = (self.dut.reg_wr_addr.value.integer // byte_lanes) * byte_lanes
@ -122,7 +122,7 @@ class TB(object):
strb = self.dut.reg_wr_strb.value.integer
if self.dut.reg_wr_en.value.integer and addr < len(self.mem):
self.dut.reg_wr_wait <= 1
self.dut.reg_wr_wait.value = 1
for k in range(10):
await RisingEdge(self.dut.clk)
@ -137,8 +137,8 @@ class TB(object):
else:
self.mem.seek(1, 1)
self.dut.reg_wr_wait <= 0
self.dut.reg_wr_ack <= 1
self.dut.reg_wr_wait.value = 0
self.dut.reg_wr_ack.value = 1
await RisingEdge(self.dut.clk)
def mem_read(self, address, length):

4
tb/axil_register/test_axil_register.py
View File

@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)