diff --git a/tb/axi_adapter/test_axi_adapter.py b/tb/axi_adapter/test_axi_adapter.py index 2cfcb8b..7c97c2f 100644 --- a/tb/axi_adapter/test_axi_adapter.py +++ b/tb/axi_adapter/test_axi_adapter.py @@ -70,10 +70,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axi_axil_adapter/test_axi_axil_adapter.py b/tb/axi_axil_adapter/test_axi_axil_adapter.py index b2b22f8..4871389 100644 --- a/tb/axi_axil_adapter/test_axi_axil_adapter.py +++ b/tb/axi_axil_adapter/test_axi_axil_adapter.py @@ -70,10 +70,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axi_cdma/test_axi_cdma.py b/tb/axi_cdma/test_axi_cdma.py index 775803b..0616bc1 100644 --- a/tb/axi_cdma/test_axi_cdma.py +++ b/tb/axi_cdma/test_axi_cdma.py @@ -80,10 +80,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -103,7 +103,7 @@ async def run_test(dut, data_in=None, idle_inserter=None, backpressure_inserter= tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - dut.enable <= 1 + dut.enable.value = 1 for length in list(range(1, byte_lanes*4+1))+[128]: for read_offset in list(range(8, 8+byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)): diff --git a/tb/axi_crossbar/test_axi_crossbar.py b/tb/axi_crossbar/test_axi_crossbar.py index 87745e6..e647a5c 100644 --- a/tb/axi_crossbar/test_axi_crossbar.py +++ b/tb/axi_crossbar/test_axi_crossbar.py @@ -84,10 +84,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axi_dma/test_axi_dma.py b/tb/axi_dma/test_axi_dma.py index 382c120..6bdc3ab 100644 --- a/tb/axi_dma/test_axi_dma.py +++ b/tb/axi_dma/test_axi_dma.py @@ -95,10 +95,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -118,7 +118,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - dut.write_enable <= 1 + dut.write_enable.value = 1 for length in list(range(1, byte_lanes*4+1))+[128]: for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)): @@ -174,7 +174,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - dut.read_enable <= 1 + dut.read_enable.value = 1 for length in list(range(1, byte_lanes*4+1))+[128]: for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)): diff --git a/tb/axi_dma_rd/test_axi_dma_rd.py b/tb/axi_dma_rd/test_axi_dma_rd.py index cfabcc1..f4813fc 100644 --- a/tb/axi_dma_rd/test_axi_dma_rd.py +++ b/tb/axi_dma_rd/test_axi_dma_rd.py @@ -82,10 +82,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -105,7 +105,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - dut.enable <= 1 + dut.enable.value = 1 for length in list(range(1, byte_lanes*4+1))+[128]: for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)): diff --git a/tb/axi_dma_wr/test_axi_dma_wr.py b/tb/axi_dma_wr/test_axi_dma_wr.py index 806750b..c2222d7 100644 --- a/tb/axi_dma_wr/test_axi_dma_wr.py +++ b/tb/axi_dma_wr/test_axi_dma_wr.py @@ -83,10 +83,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -106,7 +106,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - dut.enable <= 1 + dut.enable.value = 1 for length in list(range(1, byte_lanes*4+1))+[128]: for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)): diff --git a/tb/axi_dp_ram/test_axi_dp_ram.py b/tb/axi_dp_ram/test_axi_dp_ram.py index d789aa4..9be851e 100644 --- a/tb/axi_dp_ram/test_axi_dp_ram.py +++ b/tb/axi_dp_ram/test_axi_dp_ram.py @@ -71,13 +71,13 @@ class TB(object): self.dut.b_rst.setimmediatevalue(0) await RisingEdge(self.dut.a_clk) await RisingEdge(self.dut.a_clk) - self.dut.a_rst <= 1 - self.dut.b_rst <= 1 + self.dut.a_rst.value = 1 + self.dut.b_rst.value = 1 await RisingEdge(self.dut.a_clk) await RisingEdge(self.dut.a_clk) - self.dut.a_rst <= 0 + self.dut.a_rst.value = 0 await RisingEdge(self.dut.b_clk) - self.dut.b_rst <= 0 + self.dut.b_rst.value = 0 await RisingEdge(self.dut.a_clk) await RisingEdge(self.dut.a_clk) diff --git a/tb/axi_fifo/test_axi_fifo.py b/tb/axi_fifo/test_axi_fifo.py index 8b126e6..3e2b2d2 100644 --- a/tb/axi_fifo/test_axi_fifo.py +++ b/tb/axi_fifo/test_axi_fifo.py @@ -70,10 +70,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axi_interconnect/test_axi_interconnect.py b/tb/axi_interconnect/test_axi_interconnect.py index 3e08550..f2cc1df 100644 --- a/tb/axi_interconnect/test_axi_interconnect.py +++ b/tb/axi_interconnect/test_axi_interconnect.py @@ -78,10 +78,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axi_ram/test_axi_ram.py b/tb/axi_ram/test_axi_ram.py index 7fca201..ff46db5 100644 --- a/tb/axi_ram/test_axi_ram.py +++ b/tb/axi_ram/test_axi_ram.py @@ -64,10 +64,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axi_register/test_axi_register.py b/tb/axi_register/test_axi_register.py index 0c217e9..5441728 100644 --- a/tb/axi_register/test_axi_register.py +++ b/tb/axi_register/test_axi_register.py @@ -70,10 +70,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axil_adapter/test_axil_adapter.py b/tb/axil_adapter/test_axil_adapter.py index 5b21cff..75920cf 100644 --- a/tb/axil_adapter/test_axil_adapter.py +++ b/tb/axil_adapter/test_axil_adapter.py @@ -70,10 +70,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axil_cdc/test_axil_cdc.py b/tb/axil_cdc/test_axil_cdc.py index 70888e1..a43a1d1 100644 --- a/tb/axil_cdc/test_axil_cdc.py +++ b/tb/axil_cdc/test_axil_cdc.py @@ -72,13 +72,13 @@ class TB(object): self.dut.m_rst.setimmediatevalue(0) await RisingEdge(self.dut.s_clk) await RisingEdge(self.dut.s_clk) - self.dut.s_rst <= 1 - self.dut.m_rst <= 1 + self.dut.s_rst.value = 1 + self.dut.m_rst.value = 1 await RisingEdge(self.dut.s_clk) await RisingEdge(self.dut.s_clk) - self.dut.s_rst <= 0 + self.dut.s_rst.value = 0 await RisingEdge(self.dut.m_clk) - self.dut.m_rst <= 0 + self.dut.m_rst.value = 0 await RisingEdge(self.dut.s_clk) await RisingEdge(self.dut.s_clk) diff --git a/tb/axil_crossbar/test_axil_crossbar.py b/tb/axil_crossbar/test_axil_crossbar.py index 23ef209..396c00c 100644 --- a/tb/axil_crossbar/test_axil_crossbar.py +++ b/tb/axil_crossbar/test_axil_crossbar.py @@ -78,10 +78,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axil_dp_ram/test_axil_dp_ram.py b/tb/axil_dp_ram/test_axil_dp_ram.py index e51d19c..e376402 100644 --- a/tb/axil_dp_ram/test_axil_dp_ram.py +++ b/tb/axil_dp_ram/test_axil_dp_ram.py @@ -71,13 +71,13 @@ class TB(object): self.dut.b_rst.setimmediatevalue(0) await RisingEdge(self.dut.a_clk) await RisingEdge(self.dut.a_clk) - self.dut.a_rst <= 1 - self.dut.b_rst <= 1 + self.dut.a_rst.value = 1 + self.dut.b_rst.value = 1 await RisingEdge(self.dut.a_clk) await RisingEdge(self.dut.a_clk) - self.dut.a_rst <= 0 + self.dut.a_rst.value = 0 await RisingEdge(self.dut.b_clk) - self.dut.b_rst <= 0 + self.dut.b_rst.value = 0 await RisingEdge(self.dut.a_clk) await RisingEdge(self.dut.a_clk) diff --git a/tb/axil_interconnect/test_axil_interconnect.py b/tb/axil_interconnect/test_axil_interconnect.py index 7b055dc..219dce4 100644 --- a/tb/axil_interconnect/test_axil_interconnect.py +++ b/tb/axil_interconnect/test_axil_interconnect.py @@ -78,10 +78,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axil_ram/test_axil_ram.py b/tb/axil_ram/test_axil_ram.py index 35e651e..e69e3d3 100644 --- a/tb/axil_ram/test_axil_ram.py +++ b/tb/axil_ram/test_axil_ram.py @@ -64,10 +64,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) diff --git a/tb/axil_reg_if/test_axil_reg_if.py b/tb/axil_reg_if/test_axil_reg_if.py index 6e4d792..734d5e1 100644 --- a/tb/axil_reg_if/test_axil_reg_if.py +++ b/tb/axil_reg_if/test_axil_reg_if.py @@ -76,10 +76,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -87,15 +87,15 @@ class TB(object): byte_lanes = len(self.dut.reg_wr_strb) while True: - self.dut.reg_rd_data <= 0 - self.dut.reg_rd_wait <= 0 - self.dut.reg_rd_ack <= 0 + self.dut.reg_rd_data.value = 0 + self.dut.reg_rd_wait.value = 0 + self.dut.reg_rd_ack.value = 0 await RisingEdge(self.dut.clk) addr = (self.dut.reg_rd_addr.value.integer // byte_lanes) * byte_lanes if self.dut.reg_rd_en.value.integer and addr < len(self.mem): - self.dut.reg_rd_wait <= 1 + self.dut.reg_rd_wait.value = 1 for k in range(10): await RisingEdge(self.dut.clk) @@ -104,17 +104,17 @@ class TB(object): data = self.mem.read(byte_lanes) - self.dut.reg_rd_data <= int.from_bytes(data, 'little') - self.dut.reg_rd_wait <= 0 - self.dut.reg_rd_ack <= 1 + self.dut.reg_rd_data.value = int.from_bytes(data, 'little') + self.dut.reg_rd_wait.value = 0 + self.dut.reg_rd_ack.value = 1 await RisingEdge(self.dut.clk) async def run_reg_write(self): byte_lanes = len(self.dut.reg_wr_strb) while True: - self.dut.reg_wr_wait <= 0 - self.dut.reg_wr_ack <= 0 + self.dut.reg_wr_wait.value = 0 + self.dut.reg_wr_ack.value = 0 await RisingEdge(self.dut.clk) addr = (self.dut.reg_wr_addr.value.integer // byte_lanes) * byte_lanes @@ -122,7 +122,7 @@ class TB(object): strb = self.dut.reg_wr_strb.value.integer if self.dut.reg_wr_en.value.integer and addr < len(self.mem): - self.dut.reg_wr_wait <= 1 + self.dut.reg_wr_wait.value = 1 for k in range(10): await RisingEdge(self.dut.clk) @@ -137,8 +137,8 @@ class TB(object): else: self.mem.seek(1, 1) - self.dut.reg_wr_wait <= 0 - self.dut.reg_wr_ack <= 1 + self.dut.reg_wr_wait.value = 0 + self.dut.reg_wr_ack.value = 1 await RisingEdge(self.dut.clk) def mem_read(self, address, length): diff --git a/tb/axil_register/test_axil_register.py b/tb/axil_register/test_axil_register.py index ad8d220..01fd310 100644 --- a/tb/axil_register/test_axil_register.py +++ b/tb/axil_register/test_axil_register.py @@ -70,10 +70,10 @@ class TB(object): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk)